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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ie/76YZoc+ACZHPckXF/3pfUaltlQbCxXD5OgPvDMJQ=; b=QVCBsJH6cCXeCg0w9CLfMMxzU30TRyKPosrTH/6pY9Kd4rem8IqQX75Bs+lHfTKTwY kOh1XcgQxSFH3zLRf2vkKjxsdAVzp1pvRpbhYm4pHGmjPXgL1uNo+BCfQmZd+rhdXjlq +vB7iu0zMNhdO9lfpGaja25xugF5CdJNMO+chez2+XDiSWpwyWMCkrNGecVUoVr67b9t V7WbbKgWeNqiGvitucgeksVxMEQfXKm1kk7DQHoOjH84VSVLOSExwCC9CUTXYWJ9HOHG 4YNdFDDZxV3jezX11hGCm4PR0KrKI/k/9rJ96BRyY9zOMgTm8zi/GWhIAWbTlWBoLAhV RPFg== X-Gm-Message-State: AOAM5328hWsvCapvo6G3TumV73pNm2NxB8a43lLKipFXBiIrz9W3rbX5 2WdOp2xJNpP6/4p4iR4aGu4vZO6gj4sNjq7CSr8q7A== X-Google-Smtp-Source: ABdhPJzf2Whm2C05vdnPBQUdQW+lDfx+rOZP0y2CDhszcOAJhgtQJWlAM595+BE27JiSii4KGRj0lFNEvoDfGkGwcGQ= X-Received: by 2002:a17:906:e50:: with SMTP id q16mr38191801eji.544.1600443301141; Fri, 18 Sep 2020 08:35:01 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-11-suzuki.poulose@arm.com> In-Reply-To: <20200911084119.1080694-11-suzuki.poulose@arm.com> From: Mike Leach Date: Fri, 18 Sep 2020 16:34:50 +0100 Message-ID: Subject: Re: [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields To: Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200918_113502_744227_89A6E15B X-CRM114-Status: GOOD ( 20.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Coresight ML , Anshuman.Khandual@arm.com, Mathieu Poirier , linux-arm-kernel , Leo Yan Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > > Define the fields of the DEVARCH register for identifying > a component as an ETMv4.x unit. Going forward, we use the > DEVARCH register for the component identification, rather > than the TRCIDR3. > TRCIDR1? - but either way, we are not using this for component ID. For the AMBA path component ID is made using CID + PID + optionally if in the table UCI - which includes DEVARCH. TRCIDR1 is simply used to get the architecture version so we can be sure the driver supports it, and can adjust behaviour for version dependent elements. > Cc: Mathieu Poirier > Cc: Mike Leach > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- > drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++++++++++++++ > 2 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 40f8113191e0..34b27c26591b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -1598,8 +1598,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) > static struct amba_cs_uci_id uci_id_etm4[] = { > { > /* ETMv4 UCI data */ > - .devarch = 0x47704a13, > - .devarch_mask = 0xfff0ffff, > + .devarch = ETM_DEVARCH_ETMv4x_ARCH, > + .devarch_mask = ETM_DEVARCH_ID_MASK, > .devtype = 0x00000013, Perhaps a good time to change this to a #define constant too. I assume that if the system access is going to use the coresight architected registers for ID - it should use the same set as the AMBA path - i.e. DEVARCH + DEVTYPE. > } > }; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4044676d2385..29ffad6a5279 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -497,6 +497,24 @@ > ETM_MODE_EXCL_KERN | \ > ETM_MODE_EXCL_USER) > > +#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) > +#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) > +#define ETM_DEVARCH_PRESENT BIT(20) > +#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) > +#define ETM_DEVARCH_REVISION_SHIFT 16 > +#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) > +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 > +#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ > + (((x) & 0xfUL) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) > +#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) > +#define ETM_DEVARCH_ARCHID_ETMv4 \ > + (ETM_DEVARCH_ARCHID_ARCH_VER(4) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) > + > +#define ETM_DEVARCH_ID_MASK \ > + (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) > +#define ETM_DEVARCH_ETMv4x_ARCH \ > + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4 | ETM_DEVARCH_PRESENT) > + > #define TRCSTATR_IDLE_BIT 0 > #define TRCSTATR_PMSTABLE_BIT 1 > #define ETM_DEFAULT_ADDR_COMP 0 > -- > 2.24.1 > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel