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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NwjTcE9AB3lHB1l2CsQFQTvyIOX/+r8AdYJzECU/66k=; b=eIDWU9B7uk7aVeo1QRZIEysCjwwBodbKiG8xStB5jmoImf864V9b/gQOnk6BUpIj8w /BpFFoXjxr8xOogM8ttn0dljfODjdyfq8sMT7H7Nj4N8r3SnypAJnSvqhuPyq+IhkrNC SSvxAcjd1nwtjS4fUSGiI4f//Ft0Nrm/cy4XCngwRirIzwRpDBYAMJGCbzSKcPih91ep qu54tPUPkXfGfnbh0qBqsVY4424gX8Ylm8c54j5U4heolrAfdXhlqHPwU7i502H0lf9S 9ET5qo0dY8kgXki2w565E/PCUFK6y3K7bnGr8wpleCerqRcZng5dG+0eI54sHXjfmaOn 1FeQ== X-Gm-Message-State: AOAM533psgZCPOhI+qiowQUApofA057MMCTsS6D/acjUcQeJ6nLs+ZAs pKeq2bkgfd+/w4RxLKUSxUC8od5tk/wDBBVSFCKnBA== X-Google-Smtp-Source: ABdhPJz0RXsbLR/522U+sQlDSxlqhG40ODpQ41EJiiCzWsKIo/gVFRdlB1gDTkyVhyfrzUh+mVIY1r90zeQcaUlAodk= X-Received: by 2002:a05:6214:2d2:: with SMTP id g18mr30162630qvu.215.1593702452178; Thu, 02 Jul 2020 08:07:32 -0700 (PDT) MIME-Version: 1.0 References: <20200630173734.14057-1-will@kernel.org> <20200630173734.14057-5-will@kernel.org> <20200702145532.GB16999@willie-the-truck> In-Reply-To: <20200702145532.GB16999@willie-the-truck> From: Joel Fernandes Date: Thu, 2 Jul 2020 11:07:19 -0400 Message-ID: Subject: Re: [PATCH 04/18] alpha: Override READ_ONCE() with barriered implementation To: Will Deacon X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_160740_461928_1C525354 X-CRM114-Status: GOOD ( 34.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Michael S. Tsirkin" , Peter Zijlstra , Catalin Marinas , Jason Wang , virtualization@lists.linux-foundation.org, "Joel Fernandes \(Google\)" , Arnd Bergmann , Alan Stern , Sami Tolvanen , Matt Turner , "Cc: Android Kernel" , Marco Elver , Kees Cook , "Paul E. McKenney" , Boqun Feng , Josh Triplett , Ivan Kokshaysky , "moderated list:ARM64 PORT \(AARCH64 ARCHITECTURE\)" , Richard Henderson , Nick Desaulniers , LKML , linux-alpha@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 2, 2020 at 10:55 AM Will Deacon wrote: > On Thu, Jul 02, 2020 at 10:43:55AM -0400, Joel Fernandes wrote: > > On Tue, Jun 30, 2020 at 1:38 PM Will Deacon wrote: > > > diff --git a/arch/alpha/include/asm/barrier.h b/arch/alpha/include/asm/barrier.h > > > index 92ec486a4f9e..2ecd068d91d1 100644 > > > --- a/arch/alpha/include/asm/barrier.h > > > +++ b/arch/alpha/include/asm/barrier.h > > > - * For example, the following code would force ordering (the initial > > > - * value of "a" is zero, "b" is one, and "p" is "&a"): > > > - * > > > - * > > > - * CPU 0 CPU 1 > > > - * > > > - * b = 2; > > > - * memory_barrier(); > > > - * p = &b; q = p; > > > - * read_barrier_depends(); > > > - * d = *q; > > > - * > > > - * > > > - * because the read of "*q" depends on the read of "p" and these > > > - * two reads are separated by a read_barrier_depends(). However, > > > - * the following code, with the same initial values for "a" and "b": > > > - * > > > > Would it be Ok to keep this example in the kernel sources? I think it > > serves as good documentation and highlights the issue in the Alpha > > architecture well. > > I'd _really_ like to remove it, as I think it only serves to confuse people > on a topic that is confusing enough already. Paul's perfbook [1] already has > plenty of information about this, so I don't think we need to repeat that > here. I could add a citation, perhaps? True, and also found that LKMM docs and the memory-barriers.txt talks about it, so removing it here sounds good to me. Maybe a reference here to either documentation should be Ok. > > BTW, do you know any architecture where speculative execution of > > address-dependent loads can cause similar misorderings? That would be > > pretty insane though. In Alpha's case it is not speculation but rather > > the split local cache design as the docs mention. The reason I ask > > is it is pretty amusing that control-dependent loads do have such > > misordering issues due to speculative branch execution and I wondered > > what other games the CPUs are playing. FWIW I ran into [1] which talks > > about analogy between memory dependence and control dependence. > > I think you're asking about value prediction, and the implications it would > have on address-dependent loads where the address can itself be predicted. Yes. > I'm not aware of an CPUs where that is observable architecturally. I see. > arm64 has some load instructions that do not honour address dependencies, > but I believe that's mainly to enable alternative cache designs for things > like non-temporal and large vector loads. Good to know this, thanks. - Joel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel