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h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qJV0VVyb7OBSwrj4NQkfWBYcw+e0SGu2TpYvncrxquQ=; b=cek6pFz9tcy+okN/IT2+wP8zP9Pm5tdmdwxxStFZIoY09Oe4EGB+/S6tZqS7Q0iFd1 3Nv0ZvB1+MtvPzyRV5VW8VqqmcSWkHKX8hjxRb2CrJYFxt0qYNj7ebpUA0HOtc4EGxjW K5lSWIDSr8HEd0PvZAJ7HjQzUpkqF8/7Q/ex5XT0SOhEQOEOdb6xmjqr6AGFwWvyxPII YTgnTHz4F7b1w/M1YFxlIFzoRAWmdD2jsAHkcwIrmpUK2maFBJKrnhyaKC05EDUmYUqS Ui7iDPJhOPl8bvfO7OWn1r+XDHrUHrj9EmVuY9v8HcHMqh+l2dvMG0tX7kj39yxmuLlF SFpw== X-Gm-Message-State: APjAAAWDf53FJow0xOWRJru4DCj3d6DBOL3CCfPv+EeVLwKt3dxtH9eZ qoUf+Z+6u7gv3aXcoASfJHDOuPnL7+ulroF3Z7Lqrw== X-Google-Smtp-Source: APXvYqxN7Za8djlBzCs0iQ70yJGGaDd0xjSmac554wXuA65p9UMe7pqTUjduNocumSHig7Qa6Mhlgd8Iif02bjhVezI= X-Received: by 2002:ab0:66d2:: with SMTP id d18mr1393892uaq.101.1565109125884; Tue, 06 Aug 2019 09:32:05 -0700 (PDT) MIME-Version: 1.0 References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806143457.GF475@lakrids.cambridge.arm.com> In-Reply-To: <20190806143457.GF475@lakrids.cambridge.arm.com> From: Rob Clark Date: Tue, 6 Aug 2019 09:31:55 -0700 Message-ID: Subject: Re: [PATCH 1/2] drm: add cache support for arm64 To: Mark Rutland X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190806_093207_074229_9F141A5C X-CRM114-Status: GOOD ( 18.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Paul , Maxime Ripard , Catalin Marinas , Maarten Lankhorst , LKML , dri-devel , David Airlie , Rob Clark , linux-arm-kernel@lists.infradead.org, Daniel Vetter , Greg Kroah-Hartman , Thomas Gleixner , Will Deacon , Christoph Hellwig , Allison Randal Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Aug 6, 2019 at 7:35 AM Mark Rutland wrote: > > On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote: > > On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig wrote: > > > > > > This goes in the wrong direction. drm_cflush_* are a bad API we need to > > > get rid of, not add use of it. The reason for that is two-fold: > > > > > > a) it doesn't address how cache maintaince actually works in most > > > platforms. When talking about a cache we three fundamental operations: > > > > > > 1) write back - this writes the content of the cache back to the > > > backing memory > > > 2) invalidate - this remove the content of the cache > > > 3) write back + invalidate - do both of the above > > > > Agreed that drm_cflush_* isn't a great API. In this particular case > > (IIUC), I need wb+inv so that there aren't dirty cache lines that drop > > out to memory later, and so that I don't get a cache hit on > > uncached/wc mmap'ing. > > Is there a cacheable alias lying around (e.g. the linear map), or are > these addresses only mapped uncached/wc? > > If there's a cacheable alias, performing an invalidate isn't sufficient, > since a CPU can allocate a new (clean) entry at any point in time (e.g. > as a result of prefetching or arbitrary speculation). I *believe* that there are not alias mappings (that I don't control myself) for pages coming from shmem_file_setup()/shmem_read_mapping_page().. digging around at what dma_sync_sg_* does under the hood, it looks like it is just arch_sync_dma_for_cpu/device(), so I guess that should be sufficient for what I need. There are a few buffers that I vmap for use on kernel side, but like the userspace mmap's, the vmaps are also writecombine. BR, -R _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel