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Thu, 04 Mar 2021 10:58:57 +0000 Received: from mail-ot1-f41.google.com ([209.85.210.41]) by mrelayeu.kundenserver.de (mreue109 [213.165.67.113]) with ESMTPSA (Nemesis) id 1MfpGR-1lxg1W1vRp-00gIdW for ; Thu, 04 Mar 2021 11:58:47 +0100 Received: by mail-ot1-f41.google.com with SMTP id f33so26775988otf.11 for ; Thu, 04 Mar 2021 02:58:45 -0800 (PST) X-Gm-Message-State: AOAM532s6TpegTDeqpWny57n+X84rW32BkTtoGe9NqKfUO4FYa7hgyBo KqkV1l8SqKNrsKQlJZL2pdOOvNxySOkwsp0TUzY= X-Google-Smtp-Source: ABdhPJz1isN7a4ehcF9HHNeG9q7qKHd8/FFXnPMY8/CvMfpnQJJ0Yqd+ln/usQiWPlqPIG7JB8bFXpj71N5eEjpvbrc= X-Received: by 2002:a05:6830:1b65:: with SMTP id d5mr2952747ote.305.1614855524811; Thu, 04 Mar 2021 02:58:44 -0800 (PST) MIME-Version: 1.0 References: <1614764303-34903-1-git-send-email-tan.shaopeng@jp.fujitsu.com> <1614764303-34903-2-git-send-email-tan.shaopeng@jp.fujitsu.com> <20210304104650.GA20843@willie-the-truck> In-Reply-To: <20210304104650.GA20843@willie-the-truck> From: Arnd Bergmann Date: Thu, 4 Mar 2021 11:58:28 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC] soc: fujitsu: Add cache driver code To: Will Deacon List-Id: Cc: "tan.shaopeng@fujitsu.com" , Linux ARM , SoC Team , Catalin Marinas , Olof Johansson , "misono.tomohiro@fujitsu.com" , James Morse X-Provags-ID: V03:K1:EW5iZ0FeikJEWiO9h8AjuOZGbs/pYA1jHPvCEYteQE7cc9GjUBH 6zESZ/4jmEsuCogeTbSOCgi8m3sbASKewNip8tbkkZv6KefVaIAcLJA60vw5IILpip0kBlD xCQIscRq7KPjdu1DrFzQNEtUOBSmchVExrVvLarROe1Brfek/e+CCW+6yc/igolCsEk5/aO f2/5RbPVJ70SjSplcCCow== X-UI-Out-Filterresults: notjunk:1;V03:K0:cPKaIvgc7hs=:Q1/lRA3WgL5p5vyDdV/oiC DrYbYiiVf+UTpFKtZu7+mtvaU5At2mI8bhA5r666q9NMSmhOfaJU12pum+G20iysJYyaQv/YS h/AeIFOo9gQrySquRfJXkDeYQii+Zcurvt214F4miXEn098LavY8ppfcTN8Q5WSCvnYAUbegU fksYeW3rMcLhdk00+mAqW2qo5cbKARPLny+3kaJbXGJ2sE9p5cw0h5A9KnffNcDf4HQXfqwE1 lbu2ABavG+FBeljs3rtV5Kl0oVEz1DxSVxefnDSRBCbDCWPZg4hqYw785cTjh5L9FGb+N9P8u noMFBXUmLRZkjOk0WZu7sWDIXCujtECdgj3o8dQehG6VvtqDPCOlFEakkh4wmwiB8/KsZ69rg pODneQF0qo4mqgEc9ANspeJUD+TFEF2hBcZLA7bsovjVvCsWdauUM+1zwuGhf6CErv8qRgLYp xpEicAoI8HqtCY3pltFQHQWTT6bsUWj81LE2+0A5kK3IZJuDqyE+XLi2LNGQp05XrUXCAlzLX YWfLKz+tIqBHoJZvuZJ8coUG9YX+j1Jz5ng9V2YrbNMO3hvb+PlxzWpx3d4BduPsA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210304_105857_015806_625EF36F X-CRM114-Status: GOOD ( 23.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 4, 2021 at 11:46 AM Will Deacon wrote: > On Thu, Mar 04, 2021 at 10:34:43AM +0000, tan.shaopeng@fujitsu.com wrote: > > > On Wed, Mar 3, 2021 at 10:38 AM tan.shaopeng > > > wrote: > > > > + > > > > +config FUJITSU_CACHE > > > > + tristate "FUJITSU Cache Driver" > > > > + depends on ARM64_VHE || COMPILE_TEST > > > > + help > > > > + FUJITSU Cache Driver > > > > + > > > > + This driver offers cache functions for A64FX system. > > > > + Loading this cache driver, control registers will be set to enable > > > > + these functions, and advanced settings registers will be set by > > > default > > > > + values. After loading this driver, you can use the default values of > > > the > > > > + advanced settings registers or set the advanced settings registers > > > > + from EL0. Unloading this driver, control registers will be clear to > > > > + disable these functions. > > > > + When built as a module, this will be called as "fujitsu_cache". > > > > > > My feeling is that this code should be in arch/arm64/, as the cache > > > is generally considered part of the CPU, rather than part of the wider > > > SoC design, or something that can be controlled separately from the > > > core kernel and memory management code. > > > > Thanks for your advice. I also would like to hear the opinions from > > other soc&arm maintainers, and then consider whether to add this to > > arch/arm64/. > > Given that all of this is outside of the scope of the architecture, I don't > think that arch/arm64/ is the right place for it. Perhaps this would fit > into the resctrl rework that James has been doing for MPAM? Indeed, that sounds like a good starting point. I don't understand enough about either of the two to be sure, but it sounds like there is some overlap in functionality, and ideally we would have one user interface that can deal with all the hardware implementations (intel, arm, fujitsu and any future ones). Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel