Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM

[Arnd Bergmann <arnd@arndb.de>]

On Wed, Oct 9, 2019 at 10:46 AM Peter Zijlstra <peterz@infradead.org> wrote:
>
> On Tue, Oct 08, 2019 at 04:32:27PM +0200, Arnd Bergmann wrote:
> > diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
> > index 8b701f8e175c..6bf4964c105c 100644
> > --- a/arch/arm/include/asm/cmpxchg.h
> > +++ b/arch/arm/include/asm/cmpxchg.h
> > @@ -114,6 +114,24 @@ static inline unsigned long __xchg(unsigned long
> > x, volatile void *ptr, int size
> >         return ret;
> >  }
> >
> > +#ifdef CONFIG_CPU_V6
> > +static inline unsigned short smp_xchg16_relaxed(volatile unsigned
> > short *ptr, unsigned short x)
> > +{
> > +       unsigned short ret, tmp;
> > +       asm volatile("@ smp_xchg16_relaxed\n"
> > +       ".arch armv6k\n"
> > +       "1:     ldrexh  %0, [%3]\n"
> > +       "       strexh  %1, %2, [%3]\n"
> > +       "       teq     %1, #0\n"
> > +       "       bne     1b"
> > +               : "=&r" (ret), "=&r" (tmp)
> > +               : "r" (x), "r" (ptr)
> > +               : "memory", "cc");
> > +       return ret;
> > +}
> > +#define smp_xchg16_relaxed smp_xchg16_relaxed
> > +#endif
>
> Why is this not in __xchg() as a variant for case 2 ?

ldrexh/strexh are instructions that are only available on SMP-capable
architecture revisions (ARMv6K or higher). When building a kernel
that runs both on pre-K ARMv6 uniprocessor systems and on later
SMP systems, __xchg() can only do 32-bit  ldrex/strex.

The trick of smp_xchg16_relaxed() is to allow the 16-bit atomics
in code that can is only ever executed on SMP systems but not
the uniprocessor OMAP2 and i.MX3 chips that would trap.

      Arnd

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