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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uTaQurjF4DAEz2YA58sq1itwNB0DAFLlJ/DDxkRjQXs=; b=EsclvX/o56NzU2YLB247IIhVME0//1DjhghsPwad5em+dtZ7K2E25viuiIlvtthQxx Y1wxtLq9B0EMFbcgRFZOq0yUlw/Gg86GKn3GguIekbQzZJIYKOyEXjlNr+NFt+qm2282 OSg+OhdG/3ocH1DktFNRo32WQeOlAKfoBBt44l1OiSpaE/C1pQ6z2gerAZEAB1Y12RfK jXOD8SkGyZdKqwe0TIBWMKY0p5R+Dvkib8+dEF7BuOOSnobl4Vg8bT06FdpubeL/QTO4 GjOBGM6ekUvKJOxrd2uWP/kuHiHVo+7njGv6YQ6yzucbXY2KoSZ9uh9sTqM00yNX/48v Z4IQ== X-Gm-Message-State: APjAAAWCs2eCL6SG72WUfF771qPsfwdcwM7pZYUdOSq1VALFiv6p8DoE Fab3TImxL07F1bIp3G+zsuIfGZXbInKJ7z65PFfCWg== X-Google-Smtp-Source: APXvYqzOD8mZdWMW5nl/G9kBu3RjbewHkgd/pSd8u227vGW4RBm64bgLB0Ejnt8SWGd0xJ5w7k3raGX9tSnxFEfpahY= X-Received: by 2002:a02:3308:: with SMTP id c8mr15420974jae.103.1560771211244; Mon, 17 Jun 2019 04:33:31 -0700 (PDT) MIME-Version: 1.0 References: <20190612040933.GA18848@dc5-eodlnx05.marvell.com> <20190612093151.GA11554@brain-police> <20190614070914.GA21961@dc5-eodlnx05.marvell.com> <20190614095846.GC10506@fuggles.cambridge.arm.com> <20190614103850.GG10659@fuggles.cambridge.arm.com> <201906142026.1BC27EDB1E@keescook> <201906150654.FF4400F7C8@keescook> <201906161429.BCE1083@keescook> In-Reply-To: <201906161429.BCE1083@keescook> From: Ard Biesheuvel Date: Mon, 17 Jun 2019 13:33:19 +0200 Message-ID: Subject: Re: [RFC] Disable lockref on arm64 To: Kees Cook X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190617_043333_264897_410583AC X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "catalin.marinas@arm.com" , Jan Glauber , Will Deacon , "linux-kernel@vger.kernel.org" , Jayachandran Chandrasekharan Nair , Linus Torvalds , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, 16 Jun 2019 at 23:31, Kees Cook wrote: > > On Sat, Jun 15, 2019 at 04:18:21PM +0200, Ard Biesheuvel wrote: > > Yes, I am using the same saturation point as x86. In this example, I > > am not entirely sure I understand why it matters, though: the atomics > > guarantee that the write by CPU2 fails if CPU1 changed the value in > > the mean time, regardless of which value it wrote. > > > > I think the concern is more related to the likelihood of another CPU > > doing something nasty between the moment that the refcount overflows > > and the moment that the handler pins it at INT_MIN/2, e.g., > > > > > CPU 1 CPU 2 > > > inc() > > > load INT_MAX > > > about to overflow? > > > yes > > > > > > set to 0 > > > > > > set to INT_MIN/2 > > Ah, gotcha, but the "set to 0" is really "set to INT_MAX+1" (not zero) > if you're using the same saturation. > Of course. So there is no issue here: whatever manipulations are racing with the overflow handler can never result in the counter to unsaturate. And actually, moving the checks before the stores is not as trivial as I thought, E.g., for the LSE refcount_add case, we have " ldadd %w[i], w30, %[cval]\n" \ " adds %w[i], %w[i], w30\n" \ REFCOUNT_PRE_CHECK_ ## pre (w30)) \ REFCOUNT_POST_CHECK_ ## post \ and changing this into load/test/store defeats the purpose of using the LSE atomics in the first place. On my single core TX2, the comparative performance is as follows Baseline: REFCOUNT_TIMING test using REFCOUNT_FULL (LSE cmpxchg) 191057942484 cycles # 2.207 GHz 148447589402 instructions # 0.78 insn per cycle 86.568269904 seconds time elapsed Upper bound: ATOMIC_TIMING 116252672661 cycles # 2.207 GHz 28089216452 instructions # 0.24 insn per cycle 52.689793525 seconds time elapsed REFCOUNT_TIMING test using LSE atomics 127060259162 cycles # 2.207 GHz 0 instructions # 0.00 insn per cycle 57.243690077 seconds time elapsed _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel