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[209.85.208.178]) by smtp.gmail.com with ESMTPSA id s29sm2109200ljo.136.2021.03.22.17.49.19 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Mar 2021 17:49:19 -0700 (PDT) Received: by mail-lj1-f178.google.com with SMTP id u4so23397693ljo.6 for ; Mon, 22 Mar 2021 17:49:19 -0700 (PDT) X-Received: by 2002:a2e:2e19:: with SMTP id u25mr1335258lju.487.1616460558555; Mon, 22 Mar 2021 17:49:18 -0700 (PDT) MIME-Version: 1.0 References: <1614670085-26229-1-git-send-email-Fengquan.Chen@mediatek.com> <1614670085-26229-2-git-send-email-Fengquan.Chen@mediatek.com> In-Reply-To: <1614670085-26229-2-git-send-email-Fengquan.Chen@mediatek.com> From: Evan Benn Date: Tue, 23 Mar 2021 11:48:52 +1100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] clocksource/drivers/timer-mediatek: optimize systimer irq clear flow on Mediatek Socs To: Fengquan Chen Cc: Daniel Lezcano , Thomas Gleixner , Matthias Brugger , LKML , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" , dehui.sun@mediatek.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_004922_845454_FF36F879 X-CRM114-Status: GOOD ( 23.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 4, 2021 at 11:07 AM Fengquan Chen wrote: > > 1)ensure systimer is enabled before clear and disable interrupt, which only > for systimer in Mediatek Socs. Why does the timer need to be enabled before the interrupt can be disabled? The datasheet I have does not suggest that this is required. > > 2)clear any pending timer-irq when shutdown to keep suspend flow clean, > when use systimer as tick-broadcast timer > > Change-Id: Ia3eda83324af2fdaf5cbb3569a9bf020a11f8009 > Signed-off-by: Fengquan Chen > --- > drivers/clocksource/timer-mediatek.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c > index 9318edc..9f1f095dc 100644 > --- a/drivers/clocksource/timer-mediatek.c > +++ b/drivers/clocksource/timer-mediatek.c > @@ -75,6 +75,7 @@ > static void mtk_syst_ack_irq(struct timer_of *to) This function seems to be mis-named. It does more than just ack the irq. > { > /* Clear and disable interrupt */ > + writel(SYST_CON_EN, SYST_CON_REG(to)); This line seems to enable the timer and disable the interrupt. > writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); This line acks the interrupt and enables the timer and disables the interrupt. Are these lines both necessary? Maybe this function should just ack the interrupt without changing the other bits. > } > > @@ -111,6 +112,9 @@ static int mtk_syst_clkevt_next_event(unsigned long ticks, > > static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) > { > + /* Clear any irq */ > + mtk_syst_ack_irq(to_timer_of(clkevt)); > + > /* Disable timer */ > writel(0, SYST_CON_REG(to_timer_of(clkevt))); This is a third write to the same register, I believe all 3 writes can be combined into 1. Is that possible? > > -- > 1.8.1.1.dirty > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel