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Fri, 20 Sep 2019 08:51:02 -0700 (PDT) X-Gm-Message-State: APjAAAUvkwO1I8vCAVFpEX9p0ppmt7LhI5/1mA6ceg9NijZiguUCtgL9 L0A2p1JaDQ1Co0dM5TjPpS0ghxCUQCtJCYsv/A== X-Google-Smtp-Source: APXvYqwMIrqIhbU+PH2zwmKFyZZ7p9gmNZDVfDvJtsMY/FngbKyrGtmiBbkzWBc5h/SVux0vE5Rh9MaGgWH9K6YJIV0= X-Received: by 2002:ac8:444f:: with SMTP id m15mr4046894qtn.110.1568994661811; Fri, 20 Sep 2019 08:51:01 -0700 (PDT) MIME-Version: 1.0 References: <20190918173141.4314-1-krzk@kernel.org> <20190918173141.4314-8-krzk@kernel.org> In-Reply-To: <20190918173141.4314-8-krzk@kernel.org> From: Rob Herring Date: Fri, 20 Sep 2019 10:50:50 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 8/8] dt-bindings: pwm: Convert Samsung PWM bindings to json-schema To: Krzysztof Kozlowski X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190920_085103_387705_B9B73A56 X-CRM114-Status: GOOD ( 22.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Linux PWM List , dri-devel , Thierry Reding , linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Linux LED Subsystem , linux-samsung-soc , Herbert Xu , linux-clk , "open list:ARM/Rockchip SoC..." , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Guenter Roeck , devicetree@vger.kernel.org, LINUX-WATCHDOG , "moderated list:ARM/Mediatek SoC support" , "moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" , Matt Mackall , linux-tegra@vger.kernel.org, linux-amlogic@lists.infradead.org, Wim Van Sebroeck , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , "open list:HARDWARE RANDOM NUMBER GENERATOR CORE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 18, 2019 at 12:32 PM Krzysztof Kozlowski wrote: > > Convert Samsung PWM (S3C, S5P and Exynos SoCs) bindings to DT schema > format using json-schema. > > Signed-off-by: Krzysztof Kozlowski > > --- > > Changes since v1: > 1. Indent example with four spaces (more readable), > 2. Fix samsung,pwm-outputs after review, > 3. Remove double-quotes from clock names. > --- > .../devicetree/bindings/pwm/pwm-samsung.txt | 51 --------- > .../devicetree/bindings/pwm/pwm-samsung.yaml | 107 ++++++++++++++++++ > 2 files changed, 107 insertions(+), 51 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.txt > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > deleted file mode 100644 > index 5538de9c2007..000000000000 > --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > +++ /dev/null > @@ -1,51 +0,0 @@ > -* Samsung PWM timers > - > -Samsung SoCs contain PWM timer blocks which can be used for system clock source > -and clock event timers, as well as to drive SoC outputs with PWM signal. Each > -PWM timer block provides 5 PWM channels (not all of them can drive physical > -outputs - see SoC and board manual). > - > -Be aware that the clocksource driver supports only uniprocessor systems. > - > -Required properties: > -- compatible : should be one of following: > - samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs > - samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs > - samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs > - samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, > - Exynos4210 rev0 SoCs > - samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, > - Exynos4x12, Exynos5250 and Exynos5420 SoCs > -- reg: base address and size of register area > -- interrupts: list of timer interrupts (one interrupt per timer, starting at > - timer 0) > -- clock-names: should contain all following required clock names: > - - "timers" - PWM base clock used to generate PWM signals, > - and any subset of following optional clock names: > - - "pwm-tclk0" - first external PWM clock source, > - - "pwm-tclk1" - second external PWM clock source. > - Note that not all IP variants allow using all external clock sources. > - Refer to SoC documentation to learn which clock source configurations > - are available. > -- clocks: should contain clock specifiers of all clocks, which input names > - have been specified in clock-names property, in same order. > -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of > - the cells format. The only third cell flag supported by this binding is > - PWM_POLARITY_INVERTED. > - > -Optional properties: > -- samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular > - platform - an array of up to 5 elements being indices of PWM channels > - (from 0 to 4), the order does not matter. > - > -Example: > - pwm@7f006000 { > - compatible = "samsung,s3c6400-pwm"; > - reg = <0x7f006000 0x1000>; > - interrupt-parent = <&vic0>; > - interrupts = <23>, <24>, <25>, <27>, <28>; > - clocks = <&clock 67>; > - clock-names = "timers"; > - samsung,pwm-outputs = <0>, <1>; > - #pwm-cells = <3>; > - } > diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml > new file mode 100644 > index 000000000000..06d11faabff6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung SoC PWM timers > + > +maintainers: > + - Thierry Reding > + - Krzysztof Kozlowski > + > +description: |+ > + Samsung SoCs contain PWM timer blocks which can be used for system clock source > + and clock event timers, as well as to drive SoC outputs with PWM signal. Each > + PWM timer block provides 5 PWM channels (not all of them can drive physical > + outputs - see SoC and board manual). > + > + Be aware that the clocksource driver supports only uniprocessor systems. > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + enum: > + - samsung,s3c2410-pwm # 16-bit, S3C24xx > + - samsung,s3c6400-pwm # 32-bit, S3C64xx > + - samsung,s5p6440-pwm # 32-bit, S5P64x0 > + - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs > + - samsung,exynos4210-pwm # 32-bit, Exynos > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + description: | > + Should contain all following required clock names: > + - "timers" - PWM base clock used to generate PWM signals, > + and any subset of following optional clock names: > + - "pwm-tclk0" - first external PWM clock source, > + - "pwm-tclk1" - second external PWM clock source. > + Note that not all IP variants allow using all external clock sources. > + Refer to SoC documentation to learn which clock source configurations > + are available. > + oneOf: > + - items: > + - const: timers > + - items: > + - const: timers > + - const: pwm-tclk0 > + - items: > + - const: timers > + - const: pwm-tclk1 > + - items: > + - const: timers > + - const: pwm-tclk0 > + - const: pwm-tclk1 > + > + interrupts: > + description: > + One interrupt per timer, starting at timer 0. > + minItems: 1 > + maxItems: 5 > + > + "#pwm-cells": > + description: > + The only third cell flag supported by this binding > + is PWM_POLARITY_INVERTED. > + const: 3 > + > + samsung,pwm-outputs: > + description: > + A list of PWM channels used as PWM outputs on particular platform. > + It is an array of up to 5 elements being indices of PWM channels > + (from 0 to 4), the order does not matter. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + - uniqueItems: true > + - items: > + minimum: 0 > + maximum: 4 > + > +required: > + - clocks > + - clock-names > + - compatible > + - interrupts > + - "#pwm-cells" > + - reg additionalProperties: false should work here. And in the rng binding too. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel