Re: [PATCH 2/3] arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC

From: Ard Biesheuvel <ardb@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	 Christoph Hellwig <hch@lst.de>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: Re: [PATCH 2/3] arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC
Date: Thu, 6 May 2021 19:45:17 +0200	[thread overview]
Message-ID: <CAMj1kXHXtbN-YiBFgrVJ3XRgOMVBx4e02V7Fxj0bi1qZ1oerYg@mail.gmail.com> (raw)
In-Reply-To: <20210506132522.GC22164@arm.com>

On Thu, 6 May 2021 at 15:25, Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Thu, May 06, 2021 at 12:14:55PM +0200, Ard Biesheuvel wrote:
> > On Thu, 6 May 2021 at 11:50, Will Deacon <will@kernel.org> wrote:
> > >
> > > The only user we have of Normal Write-Through memory is in the ACPI code
> > > when mapping memory regions advertised as EFI_MEMORY_WT. Since most (all?)
> > > CPUs treat write-through as non-cacheable under the hood, don't bother
> > > with the extra memory type here and just treat EFI_MEMORY_WT the same way
> > > as EFI_MEMORY_WC by mapping it to the Normal-NC memory type instead.
> > >
> > > Cc: Ard Biesheuvel <ardb@kernel.org>
> > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > Cc: Christoph Hellwig <hch@lst.de>
> > > Signed-off-by: Will Deacon <will@kernel.org>
> >
> > I don't have any objections to this change per se, but I will point
> > out that the UEFI spec describes the MAIR encodings, paragraph 2.3.6.1
> > (in revision 2.8B). However, the paragraph in question provides no
> > context whatsoever, and so it is not clear whether it is normative,
> > and whether it applies to the boot time firmware only or to the OS as
> > well.
> >
> > So in summary, given that EFI_MEMORY_WT (which I have never seen being
> > used on ARM) should behave as expected when using the same MAIR
> > attributes as EFI_MEMORY_WC, with only a theoretical performance
> > impact, the change looks reasonable to me.
>
> In theory there's a slight difference between WT and WC/Normal-NC as
> reads are allowed to hit into the cache while for WC/Normal-NC they
> aren't (somehow implied on page B2-168 in the ARMv8 ARM G.a). Whether
> they must hit in the cache is not entirely clear, I don't think they
> have to. The mismatched aliases section doesn't guarantee coherency
> between accesses using different WC and WB attributes (point 1,
> attributes must be the same for both reads and writes). Appendix K4.1.1
> also suggest that WT could be implemented as Normal-NC.
>
> So I don't think EFI can rely on any specific WT behaviour other than
> maybe slightly better performance.
>

For the record, this mostly affects mappings created by the ACPI core,
for things like RAS handling in firmware. EFI itself is not really a
part of this, but given that ACPI lacks any way to annotate memory
types for OpRegions (as x86 does not need this), we cross reference
ACPI memory map requests with the EFI memory map to infer the right
type.

For RAS in particular, I can see how firmware might rely on
non-cacheable behavior for correctness (e.g., for publishing error
records in a way that ensures they are visible to other agents, such
as a BMC), but I still don't think treating WT as WC will make a
material difference here.

> So:
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>

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