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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>,
	 Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	 Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>,
	 Philipp Zabel <p.zabel@pengutronix.de>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	 Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	 "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
	 Linux ARM <linux-arm-kernel@lists.infradead.org>,
	 Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>
Subject: Re: [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
Date: Fri, 21 May 2021 17:04:21 +0200	[thread overview]
Message-ID: <CAMuHMdUqpycW5mkX3nNn=q9TCp9gS9EZKTs0qwUAW+T+Ggh=8A@mail.gmail.com> (raw)
In-Reply-To: <20210514192218.13022-12-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document the device tree bindings of the Renesas RZ/G2L SoC clock
> driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset

(Module Standby Mode
> +
> +maintainers:
> +  - Geert Uytterhoeven <geert+renesas@glider.be>
> +
> +description: |
> +  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP
> +  (Module Stop and Software Reset) share the same register block.
> +
> +  They provide the following functionalities:
> +    - The CPG block generates various core clocks,
> +    - The MSTP block provides two functions:
> +        1. Module Stop, providing a Clock Domain to control the clock supply
> +           to individual SoC devices,
> +        2. Reset Control, to perform a software reset of individual SoC devices.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a07g044l-cpg  # RZ/G2L

renesas,r9a07g044-cpg?

I believe it's the same block on RZ/G2L ('044l) and RZ/G2LC ('044c).

> +  '#clock-cells':
> +    description: |
> +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> +        and a core clock reference, as defined in
> +        <dt-bindings/clock/*-cpg-mssr.h>

<dt-bindings/clock/r9a07g044l-cpg.h>

> +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> +        a module number, as defined in the datasheet.

Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

> +    const: 2
> +
> +  '#power-domain-cells':
> +    description:
> +      SoC devices that are part of the CPG/MSTP Clock Domain and can be
> +      power-managed through Module Stop should refer to the CPG device node
> +      in their "power-domains" property, as documented by the generic PM Domain
> +      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
> +    const: 0
> +
> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the module number, as defined in
> +      the datasheet.

Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

> +    const: 1

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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  parent reply	other threads:[~2021-05-21 15:06 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 19:22 [PATCH 00/16] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar
2021-05-14 19:22 ` [PATCH 01/16] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar
2021-05-18  1:31   ` Rob Herring
2021-05-21 13:22   ` Geert Uytterhoeven
2021-05-21 16:54     ` Lad, Prabhakar
2021-05-27 11:29       ` Geert Uytterhoeven
2021-05-27 11:47         ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L, LC} SoC variants Lad Prabhakar
2021-05-18  1:31   ` Rob Herring
2021-05-21 13:23   ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} " Geert Uytterhoeven
2021-05-21 17:09     ` Lad, Prabhakar
2021-05-27 11:28       ` Geert Uytterhoeven
2021-05-27 11:49         ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 03/16] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar
2021-05-18  1:32   ` Rob Herring
2021-05-21 13:24   ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} for the new RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-21 13:25   ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} for the new RZ/G2{L,LC} SoC's Geert Uytterhoeven
2021-05-21 17:21     ` Lad, Prabhakar
2021-05-27 11:47       ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 05/16] arm64: defconfig: Enable ARCH_R9A07G044{L,LC} Lad Prabhakar
2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas, prr: Add new compatible string for RZ/G{L, LC, UL} Lad Prabhakar
2021-05-18  1:33   ` Rob Herring
2021-05-21 13:25   ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 07/16] soc: renesas: Add support to read LSI DEVID register Lad Prabhakar
2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas, scif: Document r9a07g044 bindings Lad Prabhakar
2021-05-18  1:33   ` Rob Herring
2021-05-21 13:26   ` [PATCH 09/16] dt-bindings: serial: renesas,scif: " Geert Uytterhoeven
2021-05-21 15:15     ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar
2021-05-21 13:26   ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-05-18  1:35   ` Rob Herring
2021-05-21 15:04   ` Geert Uytterhoeven [this message]
2021-05-21 18:42     ` Lad, Prabhakar
2021-05-27 11:51       ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar
2021-05-21 15:03   ` Geert Uytterhoeven
2021-05-21 15:19   ` Geert Uytterhoeven
2021-05-21 18:37     ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-05-21 15:02   ` Geert Uytterhoeven
2021-05-27 12:04   ` Geert Uytterhoeven
2021-05-28  7:51     ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 14/16] clk: renesas: Add support for R9A07G044L SoC Lad Prabhakar
2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-21 15:35   ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Geert Uytterhoeven
2021-05-21 18:36     ` Lad, Prabhakar
2021-05-27 11:17   ` Geert Uytterhoeven
2021-05-27 11:51     ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 16/16] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
2021-05-21 15:40   ` Geert Uytterhoeven
2021-05-21 18:21     ` Lad, Prabhakar

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