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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dGkwaq8lw7fMLDfPL6B7cGksh4Hi48p1DuxNEtaP3pU=; b=KhPIIQ9pwanCWtsqm+OlyIt0/eFBIE0oYNERpQVK3OMszYjWE+gO8bBhOuwsqXmXb5 sOPwvU1+H+h0N7/ntkjJxz56YpMIwV68CUdTEET0dFKqeE7ULj0bAdSxCMLF0Dkx5hwR 9lpa5E7+RaFJTjbCdMKbVYFGj0B1DBHqEg6iO7Sglu4cwOhHIG+b1TPDs6hwxCCxrBQG bPIEb7yWXXABlu87R5Chc5Ige996QGov5W7ehc+Ji7iB/NV4wFgRQzT5OBthN9nYzc9+ n380cuQNqC+CLRvgB6Agl/yvOAl5YdQG7JH+8K+r8680kF4cfXQLmT0uxQhX/KBDpTr/ M4nQ== X-Gm-Message-State: ANhLgQ2HVJidhqpL02aIAQaeAcuf6XW4LGXe3XBWs2vibB7JEnLXIZp1 dHUdQ6/z6XNMyt3xWiZxMMXpxOnDHrIDE0KKkOU= X-Google-Smtp-Source: ADFU+vv+kpji+ynroJiBDzsRd7WhZYytunKgmF0KXs+VSTXf5eOLwMqu0/hlD41bGO5/ir6ecQTiSgXijOGmBe/G3yA= X-Received: by 2002:a92:c008:: with SMTP id q8mr4757821ild.221.1584017681454; Thu, 12 Mar 2020 05:54:41 -0700 (PDT) MIME-Version: 1.0 References: <20200310194854.831-1-linux.amoon@gmail.com> <20200310194854.831-6-linux.amoon@gmail.com> <20200311144248.GA4455@kozik-lap> <20200312113618.GA6206@pi3> In-Reply-To: <20200312113618.GA6206@pi3> From: Anand Moon Date: Thu, 12 Mar 2020 18:24:30 +0530 Message-ID: Subject: Re: [PATCHv3 5/5] clk: samsung: exynos542x: Move FSYS subsystem clocks to its sub-CMU To: Krzysztof Kozlowski X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200312_055442_392997_578E2977 X-CRM114-Status: GOOD ( 24.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Stephen Boyd , Michael Turquette , Linux USB Mailing List , Linux Kernel , Tomasz Figa , Chanwoo Choi , Rob Herring , Kukjin Kim , Sylwester Nawrocki , Felipe Balbi , "open list:COMMON CLK FRAMEWORK" , linux-arm-kernel , Marek Szyprowski Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Thu, 12 Mar 2020 at 17:06, Krzysztof Kozlowski wrote: > > On Thu, Mar 12, 2020 at 04:04:57PM +0530, Anand Moon wrote: > > Hi Krzysztof, > > > > Thanks for your review comments. > > > > On Wed, 11 Mar 2020 at 20:12, Krzysztof Kozlowski wrote: > > > > > > On Tue, Mar 10, 2020 at 07:48:54PM +0000, Anand Moon wrote: > > > > FSYS power domain support usbdrd3, pdma and usb2 power gaiting, > > > > hence move FSYS clk setting to sub-CMU block to support power domain > > > > on/off sequences for device nodes. > > > > > > > > Signed-off-by: Anand Moon > > > > --- > > > > New patch in the series > > > > --- > > > > drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++------- > > > > 1 file changed, 34 insertions(+), 11 deletions(-) > > > > > > > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > > > > index c9e5a1fb6653..6c4c47dfcdce 100644 > > > > --- a/drivers/clk/samsung/clk-exynos5420.c > > > > +++ b/drivers/clk/samsung/clk-exynos5420.c > > > > @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { > > > > DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), > > > > DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), > > > > > > > > - /* USB3.0 */ > > > > - DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), > > > > - DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), > > > > - DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), > > > > - DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), > > > > > > According to clock diagram these are still in CMU TOP, not FSYS. > > > > > > > - > > > > /* MMC */ > > > > DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), > > > > DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), > > > > @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { > > > /> > > > > /* FSYS Block */ > > > > GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), > > > > - GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), > > > > - GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), > > > > GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), > > > > GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), > > > > GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), > > > > @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { > > > > GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), > > > > GATE(CLK_SROMC, "sromc", "aclk200_fsys2", > > > > GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), > > > > - GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), > > > > - GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), > > > > - GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), > > > > GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", > > > > SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), > > > > > > > > @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { > > > > { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ > > > > }; > > > > > > > > +/* USB3.0 */ > > > > +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = { > > > > + DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), > > > > + DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), > > > > + DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), > > > > + DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), > > > > +}; > > > > + > > > > +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = { > > > > + GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), > > > > + GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), > > > > + GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), > > > > + GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), > > > > + GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), > > > > +}; > > > > + > > > > +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = { > > > > + { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */ > > > > > > This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which > > > you are not suspending. They do not belong to this CMU. > > > > > > > Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above > > exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU, > > with this change it works as per previously. > > Wait, you should set here proper registers with proper mask. Yes I will set the proper mask for each as per the Exynos 5422 User Manual. Here is what I feel CLK_GATE_BUS_FSYS0 controls the PHY clock CLK_GATE_IP_FSYS controls the IP clock. So both these field should be part of this FSYS CMU. > > > > > Don't you need to save also parts of GATE_BUS_FSYS0? > > > > GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list > > of control register which are saved and restored during suspend and resume > > so no point in adding this here, I should drop the GATE_IP_FSYS reg > > dump over here. > > Since registers are used in separate sub CMU devices, each should > save/restore its part. Ok I will add both GATE_BUS_FSYS0 and GATE_IP_FSYS reset value over here. > > Best regards, > Krzysztof > -Anand _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel