* [PATCH 1/2] coresight: tmc-etr: Fix updating buffer in not-snapshot mode
2019-08-20 19:41 [PATCH 0/2] Coresight: Fix for v5.3-rc5 Mathieu Poirier
@ 2019-08-20 19:41 ` Mathieu Poirier
2019-08-20 19:41 ` [PATCH 2/2] coresight: tmc-etr: Fix perf_data check Mathieu Poirier
2019-08-21 19:28 ` [PATCH 0/2] Coresight: Fix for v5.3-rc5 Mathieu Poirier
2 siblings, 0 replies; 5+ messages in thread
From: Mathieu Poirier @ 2019-08-20 19:41 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Yabin Cui <yabinc@google.com>
TMC etr always copies all available data to perf aux buffer, which
may exceed the available space in perf aux buffer. It isn't suitable
for not-snapshot mode, because:
1) It may overwrite previously written data.
2) It may make the perf_event_mmap_page->aux_head report having more
or less data than the reality.
So change to only copy the latest data fitting the available space in
perf aux buffer.
Signed-off-by: Yabin Cui <yabinc@google.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 17006705287a..676dcb4cf0e2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1410,9 +1410,10 @@ static void tmc_free_etr_buffer(void *config)
* tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware
* buffer to the perf ring buffer.
*/
-static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
+static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long to_copy)
{
- long bytes, to_copy;
+ long bytes;
long pg_idx, pg_offset, src_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
@@ -1422,8 +1423,7 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset;
- to_copy = etr_buf->len;
+ src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1434,6 +1434,8 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
* 3) what is available in the destination page.
* in one iteration.
*/
+ if (src_offset >= etr_buf->size)
+ src_offset -= etr_buf->size;
bytes = tmc_etr_buf_get_data(etr_buf, src_offset, to_copy,
&src_buf);
if (WARN_ON_ONCE(bytes <= 0))
@@ -1454,8 +1456,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
/* Move source pointers */
src_offset += bytes;
- if (src_offset >= etr_buf->size)
- src_offset -= etr_buf->size;
}
}
@@ -1501,7 +1501,11 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
- tmc_etr_sync_perf_buffer(etr_perf);
+ if (!etr_perf->snapshot && size > handle->size) {
+ size = handle->size;
+ lost = true;
+ }
+ tmc_etr_sync_perf_buffer(etr_perf, size);
/*
* In snapshot mode we simply increment the head by the number of byte
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] coresight: tmc-etr: Fix perf_data check
2019-08-20 19:41 [PATCH 0/2] Coresight: Fix for v5.3-rc5 Mathieu Poirier
2019-08-20 19:41 ` [PATCH 1/2] coresight: tmc-etr: Fix updating buffer in not-snapshot mode Mathieu Poirier
@ 2019-08-20 19:41 ` Mathieu Poirier
2019-08-21 19:28 ` [PATCH 0/2] Coresight: Fix for v5.3-rc5 Mathieu Poirier
2 siblings, 0 replies; 5+ messages in thread
From: Mathieu Poirier @ 2019-08-20 19:41 UTC (permalink / raw)
To: gregkh; +Cc: linux-arm-kernel
From: Yabin Cui <yabinc@google.com>
When tracing etm data of multiple threads on multiple cpus through
perf interface, each cpu has a unique etr_perf_buffer while sharing
the same etr device. There is no guarantee that the last cpu starts
etm tracing also stops last. This makes perf_data check fail.
Fix it by checking etr_buf instead of etr_perf_buffer.
Also move the code setting and clearing perf_buf to more suitable
places.
Fixes: 3147da92a8a8 ("coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios")
Signed-off-by: Yabin Cui <yabinc@google.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 8 ++++----
drivers/hwtracing/coresight/coresight-tmc.h | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 676dcb4cf0e2..ba644f444d4c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1484,7 +1484,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
goto out;
}
- if (WARN_ON(drvdata->perf_data != etr_perf)) {
+ if (WARN_ON(drvdata->perf_buf != etr_buf)) {
lost = true;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
goto out;
@@ -1496,8 +1496,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
tmc_sync_etr_buf(drvdata);
CS_LOCK(drvdata->base);
- /* Reset perf specific data */
- drvdata->perf_data = NULL;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
@@ -1560,7 +1558,6 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
}
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
- drvdata->perf_data = etr_perf;
/*
* No HW configuration is needed if the sink is already in
@@ -1576,6 +1573,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
/* Associate with monitored process. */
drvdata->pid = pid;
drvdata->mode = CS_MODE_PERF;
+ drvdata->perf_buf = etr_perf->etr_buf;
atomic_inc(csdev->refcnt);
}
@@ -1621,6 +1619,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
/* Dissociate from monitored process. */
drvdata->pid = -1;
drvdata->mode = CS_MODE_DISABLED;
+ /* Reset perf specific data */
+ drvdata->perf_buf = NULL;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 1ed50411cc3c..f9a0c95e9ba2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -178,8 +178,8 @@ struct etr_buf {
* device configuration register (DEVID)
* @idr: Holds etr_bufs allocated for this ETR.
* @idr_mutex: Access serialisation for idr.
- * @perf_data: PERF buffer for ETR.
- * @sysfs_data: SYSFS buffer for ETR.
+ * @sysfs_buf: SYSFS buffer for ETR.
+ * @perf_buf: PERF buffer for ETR.
*/
struct tmc_drvdata {
void __iomem *base;
@@ -202,7 +202,7 @@ struct tmc_drvdata {
struct idr idr;
struct mutex idr_mutex;
struct etr_buf *sysfs_buf;
- void *perf_data;
+ struct etr_buf *perf_buf;
};
struct etr_buf_operations {
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Coresight: Fix for v5.3-rc5
2019-08-20 19:41 [PATCH 0/2] Coresight: Fix for v5.3-rc5 Mathieu Poirier
2019-08-20 19:41 ` [PATCH 1/2] coresight: tmc-etr: Fix updating buffer in not-snapshot mode Mathieu Poirier
2019-08-20 19:41 ` [PATCH 2/2] coresight: tmc-etr: Fix perf_data check Mathieu Poirier
@ 2019-08-21 19:28 ` Mathieu Poirier
2019-08-28 20:25 ` Greg KH
2 siblings, 1 reply; 5+ messages in thread
From: Mathieu Poirier @ 2019-08-21 19:28 UTC (permalink / raw)
To: Greg KH; +Cc: linux-arm-kernel
On Tue, 20 Aug 2019 at 13:41, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> Good day,
>
> Please see if you can add the following fix to the current cycle. If
> you think it is a little late I'll simply lump them with the set I
> have for v5.4.
I found an issue with a corner case - please ignore this request.
>
> Applies cleanly to your char-misc-linus (d1abaeb3be7b) branch.
>
> Thanks,
> Mathieu
>
>
> Yabin Cui (2):
> coresight: tmc-etr: Fix updating buffer in not-snapshot mode
> coresight: tmc-etr: Fix perf_data check
>
> .../hwtracing/coresight/coresight-tmc-etr.c | 26 +++++++++++--------
> drivers/hwtracing/coresight/coresight-tmc.h | 6 ++---
> 2 files changed, 18 insertions(+), 14 deletions(-)
>
> --
> 2.17.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread