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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3EmRLO8wo/JIqbrGKJX2hVLR7XPZ2EAWf5gJTXryBMo=; b=f0UGWF4SgLan8PUyWyZHhGNzSM3qxv34DNyx2pvbrwu+9lsC3k0Fi0uXU/itFSlyD0 HFuF9xIDKS3Q6gas17zs9yxojhaH7lzGOUCZSqrSfSjGu+GrYQokGsWz2ufgPcV+Nsyg r9aulOnIbgQE0h4/UkaEeClrNwB8UPVCx4HSEMXC6QzaUwU1Hkm06RX23k7sjmnv5jZQ U0qLPrcdRhoCMd1aeYaOwRavhiAFRapwn+w8BuGxo25YAb2rMmVl9SQkWTsUb9t8Vlpw zc41KOB3StdIuTwCmrC3rUWZ1CFmXk0mARqfoDQGLnhKTnHzIe+Z39icfuK05eN2gEhN e/Gg== X-Gm-Message-State: APjAAAVzmvnfFdL6uyGKyAPgKAMKmAQqzGSiRSBKN8RFfSxwl1RQwNSm oVi3CosyoXtEQkNieNxK7IlgNe7crBMsb1hJoLpDrA== X-Google-Smtp-Source: APXvYqzU3qiolDAJ/GjAXoKheTYvXHwYgRozBGE3tHk3MjFJDY3gAx485Umb1ZDNCbkUawOy1hyftTdLRSk86YK6bHw= X-Received: by 2002:a5d:8908:: with SMTP id b8mr8466207ion.237.1566928684877; Tue, 27 Aug 2019 10:58:04 -0700 (PDT) MIME-Version: 1.0 References: <20190819205720.24457-1-mike.leach@linaro.org> <20190819205720.24457-4-mike.leach@linaro.org> <20190826225949.GC24690@xps15> In-Reply-To: From: Mathieu Poirier Date: Tue, 27 Aug 2019 11:57:53 -0600 Message-ID: Subject: Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters To: Mike Leach X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190827_105807_492264_25C42544 X-CRM114-Status: GOOD ( 27.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Coresight ML , linux-arm-kernel , "Suzuki K. Poulose" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 27 Aug 2019 at 04:55, Mike Leach wrote: > > Hi Mathieu, > > On Mon, 26 Aug 2019 at 23:59, Mathieu Poirier > wrote: > > > > On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote: > > > TRCACATRn registers have match bits for secure and non-secure exception > > > levels which are not accessible by the sysfs API. > > > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. > > > > > > Signed-off-by: Mike Leach > > > --- > > > .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++++ > > > 1 file changed, 39 insertions(+) > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > > > index fa1d6a938f6c..7eab5d7d0b62 100644 > > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > > > @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev, > > > } > > > static DEVICE_ATTR_RW(addr_context); > > > > > > +static ssize_t addr_exlevel_s_ns_show(struct device *dev, > > > + struct device_attribute *attr, > > > + char *buf) > > > +{ > > > + u8 idx; > > > + unsigned long val; > > > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > > > + struct etmv4_config *config = &drvdata->config; > > > + > > > + spin_lock(&drvdata->spinlock); > > > + idx = config->addr_idx; > > > + val = BMVAL(config->addr_acc[idx], 14, 8); > > > + spin_unlock(&drvdata->spinlock); > > > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > > > +} > > > + > > > +static ssize_t addr_exlevel_s_ns_store(struct device *dev, > > > + struct device_attribute *attr, > > > + const char *buf, size_t size) > > > +{ > > > + u8 idx; > > > + unsigned long val; > > > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > > > + struct etmv4_config *config = &drvdata->config; > > > + > > > + if (kstrtoul(buf, 16, &val)) > > > + return -EINVAL; > > > + > > > + spin_lock(&drvdata->spinlock); > > > + idx = config->addr_idx; > > > + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */ > > > + config->addr_acc[idx] &= ~(GENMASK(14, 8)); > > > + config->addr_acc[idx] |= (val << 8); > > > + spin_unlock(&drvdata->spinlock); > > > + return size; > > > +} > > > +static DEVICE_ATTR_RW(addr_exlevel_s_ns); > > > + > > > static ssize_t seq_idx_show(struct device *dev, > > > struct device_attribute *attr, > > > char *buf) > > > @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = { > > > &dev_attr_addr_stop.attr, > > > &dev_attr_addr_ctxtype.attr, > > > &dev_attr_addr_context.attr, > > > + &dev_attr_addr_exlevel_s_ns.attr, > > > &dev_attr_seq_idx.attr, > > > &dev_attr_seq_state.attr, > > > &dev_attr_seq_event.attr, > > > > I'm ok with this patch but the new entry needs to be documented in [1]. > > It is in a later patch. Very well > > > But > > before moving forward with that I'm wondering if this is the way to go. Would > > it be better to consolidate type, ctxtype, context and exlevel_s_ns in a single > > entry, say addr_acc_type? We'd shed a fair amount of code and make it more > > simple for users to configure. > > > > It will mean the user has less writes to do - but is it really simpler > to understand? > > At present each feature takes the input value and interprets / shifts > it to set the relevant bits in the address comparator control > registers (context type being a string input rather than bit values). > > The alternative is to require the user to understand the bit values - > which they may well do if they are referring to the ETM docs to > program in this detail, and provide a correct input value for their > requirements. > > My addition adds to the API, rather than changes it, but if you prefer > we could go with an update to a single feature to control this value > in the comparator control registers. I am definitely not strongly opinionated on this - it is an idea I wanted to float by you. Since you don't seem to have a strong position either we can just carry on with this patch and revisit in the future if need be. > > Mike > > > > > [1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > > > > -- > > > 2.17.1 > > > > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel