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Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Kajol Jain , Andi Kleen , James Clark , Andrew Kilroy , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220520_090302_647230_9719503D X-CRM114-Status: GOOD ( 17.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 17, 2022 at 6:59 AM Nick Forrington wrote: > > Categorise and add missing PMU events for Cortex-A57/A72, based on: > https://github.com/ARM-software/data/blob/master/pmu/cortex-a57.json > https://github.com/ARM-software/data/blob/master/pmu/cortex-a72.json > > These contain the same events, and are based on the Arm Technical > Reference Manuals for Cortex-A57 and Cortex-A72. > > Signed-off-by: Nick Forrington Acked-by: Ian Rogers Thanks, Ian > --- > .../arch/arm64/arm/cortex-a57-a72/branch.json | 17 ++ > .../arch/arm64/arm/cortex-a57-a72/bus.json | 29 +++ > .../arch/arm64/arm/cortex-a57-a72/cache.json | 80 ++++++++ > .../arm/cortex-a57-a72/core-imp-def.json | 179 ------------------ > .../arm64/arm/cortex-a57-a72/exception.json | 47 +++++ > .../arm64/arm/cortex-a57-a72/instruction.json | 68 +++++++ > .../arch/arm64/arm/cortex-a57-a72/memory.json | 20 ++ > 7 files changed, 261 insertions(+), 179 deletions(-) > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json > delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json > create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/memory.json > > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json > new file mode 100644 > index 000000000000..2f2d137f5f55 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json > @@ -0,0 +1,17 @@ > +[ > + { > + "ArchStdEvent": "BR_MIS_PRED" > + }, > + { > + "ArchStdEvent": "BR_PRED" > + }, > + { > + "ArchStdEvent": "BR_IMMED_SPEC" > + }, > + { > + "ArchStdEvent": "BR_RETURN_SPEC" > + }, > + { > + "ArchStdEvent": "BR_INDIRECT_SPEC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json > new file mode 100644 > index 000000000000..31505994c06c > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json > @@ -0,0 +1,29 @@ > +[ > + { > + "ArchStdEvent": "CPU_CYCLES" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS" > + }, > + { > + "ArchStdEvent": "BUS_CYCLES" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_RD" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_WR" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_SHARED" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_NORMAL" > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_PERIPH" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json > new file mode 100644 > index 000000000000..1bd59e7d982b > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json > @@ -0,0 +1,80 @@ > +[ > + { > + "ArchStdEvent": "L1I_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L1D_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL" > + }, > + { > + "ArchStdEvent": "L1I_CACHE" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L2D_CACHE" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_REFILL" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WB" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_RD" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WR" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_RD" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_WR" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" > + }, > + { > + "ArchStdEvent": "L1D_CACHE_INVAL" > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL_RD" > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL_WR" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_RD" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WR" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_REFILL_RD" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_REFILL_WR" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" > + }, > + { > + "ArchStdEvent": "L2D_CACHE_INVAL" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json > deleted file mode 100644 > index 543c7692677a..000000000000 > --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json > +++ /dev/null > @@ -1,179 +0,0 @@ > -[ > - { > - "ArchStdEvent": "L1D_CACHE_RD" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_WR" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_REFILL_RD" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_REFILL_WR" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_WB_VICTIM" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_WB_CLEAN" > - }, > - { > - "ArchStdEvent": "L1D_CACHE_INVAL" > - }, > - { > - "ArchStdEvent": "L1D_TLB_REFILL_RD" > - }, > - { > - "ArchStdEvent": "L1D_TLB_REFILL_WR" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_RD" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_WR" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_REFILL_RD" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_REFILL_WR" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_WB_VICTIM" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_WB_CLEAN" > - }, > - { > - "ArchStdEvent": "L2D_CACHE_INVAL" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_RD" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_WR" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_SHARED" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_NORMAL" > - }, > - { > - "ArchStdEvent": "BUS_ACCESS_PERIPH" > - }, > - { > - "ArchStdEvent": "MEM_ACCESS_RD" > - }, > - { > - "ArchStdEvent": "MEM_ACCESS_WR" > - }, > - { > - "ArchStdEvent": "UNALIGNED_LD_SPEC" > - }, > - { > - "ArchStdEvent": "UNALIGNED_ST_SPEC" > - }, > - { > - "ArchStdEvent": "UNALIGNED_LDST_SPEC" > - }, > - { > - "ArchStdEvent": "LDREX_SPEC" > - }, > - { > - "ArchStdEvent": "STREX_PASS_SPEC" > - }, > - { > - "ArchStdEvent": "STREX_FAIL_SPEC" > - }, > - { > - "ArchStdEvent": "LD_SPEC" > - }, > - { > - "ArchStdEvent": "ST_SPEC" > - }, > - { > - "ArchStdEvent": "LDST_SPEC" > - }, > - { > - "ArchStdEvent": "DP_SPEC" > - }, > - { > - "ArchStdEvent": "ASE_SPEC" > - }, > - { > - "ArchStdEvent": "VFP_SPEC" > - }, > - { > - "ArchStdEvent": "PC_WRITE_SPEC" > - }, > - { > - "ArchStdEvent": "CRYPTO_SPEC" > - }, > - { > - "ArchStdEvent": "BR_IMMED_SPEC" > - }, > - { > - "ArchStdEvent": "BR_RETURN_SPEC" > - }, > - { > - "ArchStdEvent": "BR_INDIRECT_SPEC" > - }, > - { > - "ArchStdEvent": "ISB_SPEC" > - }, > - { > - "ArchStdEvent": "DSB_SPEC" > - }, > - { > - "ArchStdEvent": "DMB_SPEC" > - }, > - { > - "ArchStdEvent": "EXC_UNDEF" > - }, > - { > - "ArchStdEvent": "EXC_SVC" > - }, > - { > - "ArchStdEvent": "EXC_PABORT" > - }, > - { > - "ArchStdEvent": "EXC_DABORT" > - }, > - { > - "ArchStdEvent": "EXC_IRQ" > - }, > - { > - "ArchStdEvent": "EXC_FIQ" > - }, > - { > - "ArchStdEvent": "EXC_SMC" > - }, > - { > - "ArchStdEvent": "EXC_HVC" > - }, > - { > - "ArchStdEvent": "EXC_TRAP_PABORT" > - }, > - { > - "ArchStdEvent": "EXC_TRAP_DABORT" > - }, > - { > - "ArchStdEvent": "EXC_TRAP_OTHER" > - }, > - { > - "ArchStdEvent": "EXC_TRAP_IRQ" > - }, > - { > - "ArchStdEvent": "EXC_TRAP_FIQ" > - }, > - { > - "ArchStdEvent": "RC_LD_SPEC" > - }, > - { > - "ArchStdEvent": "RC_ST_SPEC" > - } > -] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json > new file mode 100644 > index 000000000000..344a2d552ad5 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json > @@ -0,0 +1,47 @@ > +[ > + { > + "ArchStdEvent": "EXC_TAKEN" > + }, > + { > + "ArchStdEvent": "MEMORY_ERROR" > + }, > + { > + "ArchStdEvent": "EXC_UNDEF" > + }, > + { > + "ArchStdEvent": "EXC_SVC" > + }, > + { > + "ArchStdEvent": "EXC_PABORT" > + }, > + { > + "ArchStdEvent": "EXC_DABORT" > + }, > + { > + "ArchStdEvent": "EXC_IRQ" > + }, > + { > + "ArchStdEvent": "EXC_FIQ" > + }, > + { > + "ArchStdEvent": "EXC_SMC" > + }, > + { > + "ArchStdEvent": "EXC_HVC" > + }, > + { > + "ArchStdEvent": "EXC_TRAP_PABORT" > + }, > + { > + "ArchStdEvent": "EXC_TRAP_DABORT" > + }, > + { > + "ArchStdEvent": "EXC_TRAP_OTHER" > + }, > + { > + "ArchStdEvent": "EXC_TRAP_IRQ" > + }, > + { > + "ArchStdEvent": "EXC_TRAP_FIQ" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json > new file mode 100644 > index 000000000000..e42486d406b3 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json > @@ -0,0 +1,68 @@ > +[ > + { > + "ArchStdEvent": "SW_INCR" > + }, > + { > + "ArchStdEvent": "INST_RETIRED" > + }, > + { > + "ArchStdEvent": "EXC_RETURN" > + }, > + { > + "ArchStdEvent": "CID_WRITE_RETIRED" > + }, > + { > + "ArchStdEvent": "INST_SPEC" > + }, > + { > + "ArchStdEvent": "TTBR_WRITE_RETIRED" > + }, > + { > + "ArchStdEvent": "LDREX_SPEC" > + }, > + { > + "ArchStdEvent": "STREX_PASS_SPEC" > + }, > + { > + "ArchStdEvent": "STREX_FAIL_SPEC" > + }, > + { > + "ArchStdEvent": "LD_SPEC" > + }, > + { > + "ArchStdEvent": "ST_SPEC" > + }, > + { > + "ArchStdEvent": "LDST_SPEC" > + }, > + { > + "ArchStdEvent": "DP_SPEC" > + }, > + { > + "ArchStdEvent": "ASE_SPEC" > + }, > + { > + "ArchStdEvent": "VFP_SPEC" > + }, > + { > + "ArchStdEvent": "PC_WRITE_SPEC" > + }, > + { > + "ArchStdEvent": "CRYPTO_SPEC" > + }, > + { > + "ArchStdEvent": "ISB_SPEC" > + }, > + { > + "ArchStdEvent": "DSB_SPEC" > + }, > + { > + "ArchStdEvent": "DMB_SPEC" > + }, > + { > + "ArchStdEvent": "RC_LD_SPEC" > + }, > + { > + "ArchStdEvent": "RC_ST_SPEC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/memory.json > new file mode 100644 > index 000000000000..e3d08f1f7c92 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/memory.json > @@ -0,0 +1,20 @@ > +[ > + { > + "ArchStdEvent": "MEM_ACCESS" > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_RD" > + }, > + { > + "ArchStdEvent": "MEM_ACCESS_WR" > + }, > + { > + "ArchStdEvent": "UNALIGNED_LD_SPEC" > + }, > + { > + "ArchStdEvent": "UNALIGNED_ST_SPEC" > + }, > + { > + "ArchStdEvent": "UNALIGNED_LDST_SPEC" > + } > +] > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel