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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QE8OHLLcshoqgjao9rxTR2B1cn1gmKyp5nFcvuAzyYM=; b=tp+Tc9OPwjTtl7o9zbb7TsoIoF9aX+TeRa9GBH0S9r1Klsy+gegER3yMbjxCJET0Nl 3NpAbyHhxtFttlo8aQnAe1Xp+QbKc4rg0uJC7Qw9BahZKlK8YOQ5yFxxccjLjcp6TqoR +lH2sKnf3s+zeSOyE3D0e/NY0SYj8+HfXUCouU4o9X8VQuS9M7faPkPvQbia0JWFFXs2 LLhipqPFWZ7D55nNg92GIyOXnCrGFJ2I89evI39wJDJnB1p9C0gTvHl8W4UkDKpfrSoS UXjo344Cq34EbivPFX5ooZ0Wa5YeOHmb2BuLz/9TGF+V38kPYF9EXPrRx0fUDX+dmkbG 53YA== X-Gm-Message-State: AOAM533FxGuZIR0YU1sfYOF3M03kVmNxhiUC45SZPKpDHzVdMQB5emQH 02ldtzxP50EOB5cuOY5emXdVsA7G1PFJI9WErKO9WA== X-Google-Smtp-Source: ABdhPJxW3PRcgihH+QhiZOdYzkdNBQPK1MQvkyo/5kU829snF+RDUnnYIRaeoeosnQLf5x/uy3/9W6WqD+wG+F7Wjt8= X-Received: by 2002:a67:ec9a:: with SMTP id h26mr7259024vsp.34.1601901704719; Mon, 05 Oct 2020 05:41:44 -0700 (PDT) MIME-Version: 1.0 References: <20200930083120.11971-1-wenbin.mei@mediatek.com> <20200930083120.11971-2-wenbin.mei@mediatek.com> In-Reply-To: <20200930083120.11971-2-wenbin.mei@mediatek.com> From: Ulf Hansson Date: Mon, 5 Oct 2020 14:41:08 +0200 Message-ID: Subject: Re: [PATCH v3 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema To: Wenbin Mei X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201005_084147_160256_AE8E5F13 X-CRM114-Status: GOOD ( 18.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: DTML , srv_heupstream , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Chaotian Jing , Matthias Brugger , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [...] > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > new file mode 100644 > index 000000000000..7f89cbdc52a5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > @@ -0,0 +1,168 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MTK MSDC Storage Host Controller Binding > + > +maintainers: > + - Chaotian Jing > + - Wenbin Mei > + > +allOf: > + - $ref: mmc-controller.yaml# > + > +properties: > + compatible: > + oneOf: > + - enum: > + - mediatek,mt2701-mmc > + - mediatek,mt2712-mmc > + - mediatek,mt6779-mmc > + - mediatek,mt7620-mmc > + - mediatek,mt7622-mmc > + - mediatek,mt8135-mmc > + - mediatek,mt8173-mmc > + - mediatek,mt8183-mmc > + - mediatek,mt8516-mmc > + - items: > + - const: mediatek,mt7623-mmc > + - const: mediatek,mt2701-mmc > + > + clocks: > + description: > + Should contain phandle for the clock feeding the MMC controller. > + minItems: 2 > + maxItems: 4 > + items: > + - description: source clock (required). > + - description: HCLK which used for host (required). > + - description: independent source clock gate (required for MT2712). > + - description: bus clock used for internal register access (required for MT2712 MSDC0/3). > + > + clock-names: > + minItems: 2 > + maxItems: 4 > + items: > + - const: source > + - const: hclk > + - const: source_cg > + - const: bus_clk > + > + pinctrl-names: > + items: > + - const: default > + - const: state_uhs > + > + pinctrl-0: > + description: > + should contain default/high speed pin ctrl. > + maxItems: 1 > + > + pinctrl-1: > + description: > + should contain uhs mode pin ctrl. > + maxItems: 1 > + > + vmmc-supply: > + description: > + power to the Core. > + maxItems: 1 > + > + vqmmc-supply: > + description: > + power to the IO. > + maxItems: 1 The vmmc and vqmmc are described in the mmc-controller.yaml, so shouldn't be needed here. > + > + assigned-clocks: > + description: > + PLL of the source clock. > + maxItems: 1 > + > + assigned-clock-parents: > + description: > + parent of source clock, used for HS400 mode to get 400Mhz source clock. > + maxItems: 1 > + > + hs400-ds-delay: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + HS400 DS delay setting. > + minimum: 0 > + maximum: 0xffffffff > + > + mediatek,hs200-cmd-int-delay: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + HS200 command internal delay setting. > + This field has total 32 stages. > + The value is an integer from 0 to 31. > + minimum: 0 > + maximum: 31 > + > + mediatek,hs400-cmd-int-delay: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + HS400 command internal delay setting. > + This field has total 32 stages. > + The value is an integer from 0 to 31. > + minimum: 0 > + maximum: 31 > + > + mediatek,hs400-cmd-resp-sel-rising: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + HS400 command response sample selection. > + If present, HS400 command responses are sampled on rising edges. > + If not present, HS400 command responses are sampled on falling edges. > + > + mediatek,latch-ck: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Some SoCs do not support enhance_rx, need set correct latch-ck to avoid > + data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. > + if not present, default value is 0. > + applied to compatible "mediatek,mt2701-mmc". > + minimum: 0 > + maximum: 7 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: hrst > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names According to the current bindings, the vmmc/vqmmc supplies and the pinctrls are required as well. I assume you should add them here too!? [...] Kind regards Uffe _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel