From: yunhui.cui@nxp.com (Yunhui Cui)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR
Date: Thu, 30 Jun 2016 01:54:14 +0000 [thread overview]
Message-ID: <DB5PR0401MB191200E18A336E0BE5318D1694240@DB5PR0401MB1912.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com>
Hi Brian and Han,
Could you please give me some comments about this patch set v2 ?
Thanks
> -----Original Message-----
> From: Yunhui Cui [mailto:B56489 at freescale.com]
> Sent: Friday, April 22, 2016 2:40 PM
> To: dwmw2 at infradead.org; computersforpeace at gmail.com;
> han.xu at freescale.com
> Cc: linux-kernel at vger.kernel.org; linux-mtd at lists.infradead.org; linux-
> arm-kernel at lists.infradead.org; Yao Yuan; Yunhui Cui
> Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-
> NOR
>
> We can get the read/write/erase opcode from the spi nor framework
> directly. This patch uses the information stored in the SPI-NOR to remove
> the hardcode in the fsl_qspi_init_lut().
>
> Signed-off-by: Yunhui Cui <B56489@freescale.com>
> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> ---
> drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++---------------------
> ------
> 1 file changed, 12 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-
> quadspi.c
> index 9ab2b51..517ffe2 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> void __iomem *base = q->iobase;
> int rxfifo = q->devtype_data->rxfifo;
> u32 lut_base;
> - u8 cmd, addrlen, dummy;
> int i;
>
> + struct spi_nor *nor = &q->nor[0];
> + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
> + u8 read_op = nor->read_opcode;
> + u8 read_dm = nor->read_dummy;
> +
> fsl_qspi_unlock_lut(q);
>
> /* Clear all the LUT table */
> @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> /* Quad Read */
> lut_base = SEQID_QUAD_READ * 4;
>
> - if (q->nor_size <= SZ_16M) {
> - cmd = SPINOR_OP_READ_1_1_4;
> - addrlen = ADDR24BIT;
> - dummy = 8;
> - } else {
> - /* use the 4-byte address */
> - cmd = SPINOR_OP_READ_1_1_4;
> - addrlen = ADDR32BIT;
> - dummy = 8;
> - }
> -
> - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
> base + QUADSPI_LUT(lut_base));
> - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4,
> rxfifo),
> + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
> + LUT1(FSL_READ, PAD4, rxfifo),
> base + QUADSPI_LUT(lut_base + 1));
>
> /* Write enable */
> @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> /* Page Program */
> lut_base = SEQID_PP * 4;
>
> - if (q->nor_size <= SZ_16M) {
> - cmd = SPINOR_OP_PP;
> - addrlen = ADDR24BIT;
> - } else {
> - /* use the 4-byte address */
> - cmd = SPINOR_OP_PP;
> - addrlen = ADDR32BIT;
> - }
> -
> - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
> + LUT1(ADDR, PAD1, addrlen),
> base + QUADSPI_LUT(lut_base));
> qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
> base + QUADSPI_LUT(lut_base + 1));
> @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> /* Erase a sector */
> lut_base = SEQID_SE * 4;
>
> - cmd = q->nor[0].erase_opcode;
> - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
> -
> - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
> + LUT1(ADDR, PAD1, addrlen),
> base + QUADSPI_LUT(lut_base));
>
> /* Erase the whole chip */
> --
> 2.1.0.27.g96db324
next prev parent reply other threads:[~2016-06-30 1:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-22 6:39 [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 2/9] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 3/9] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash Yunhui Cui
2016-07-21 19:35 ` Han Xu
2016-08-06 14:27 ` Jagan Teki
2016-08-17 8:57 ` Yunhui Cui
2016-08-15 18:02 ` Li Yang
2016-08-17 9:07 ` Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash command conflict Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Yunhui Cui
2016-04-22 6:39 ` [PATCH v2 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Yunhui Cui
2016-06-30 1:54 ` Yunhui Cui [this message]
2016-07-21 5:58 ` [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
2016-07-21 17:09 ` Brian Norris
2016-07-21 19:34 ` Han Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=DB5PR0401MB191200E18A336E0BE5318D1694240@DB5PR0401MB1912.eurprd04.prod.outlook.com \
--to=yunhui.cui@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).