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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Thomas, Thanks for the review. Please see my inline replies. > -----Original Message----- > From: Thomas Gleixner > Sent: Thursday, February 13, 2020 5:31 PM > To: Mubin Usman Sayyed ; > jason@lakedaemon.net; maz@kernel.org; Michal Simek > ; linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org; Siva Durga Prasad Paladugu > ; Anirudha Sarangi ; Mubin > Usman Sayyed > Subject: Re: [PATCH v3] irqchip: xilinx: Add support for multiple instances > > Mubin, > > Mubin Usman Sayyed writes: > > > From: Mubin Sayyed > > > > This patch adds support for multiple instances of > > git grep 'This patch' Documentation/process/submitting-patches.rst [Mubin]: I will re-phrase it in next version. > > > xilinx interrupt controller. Below configurations are supported by > > driver, > > > > - peripheral->xilinx-intc->xilinx-intc->gic > > - peripheral->xilinx-intc->xilinx-intc > > This is really not much of an explanation. [Mubin]: Will elaborate in next version > > > Signed-off-by: Anirudha Sarangi > > Signed-off-by: Mubin Sayyed > > This Signed-off-by chain is incorrect. See chapter 11 and 12 in the same > document. [Mubin]: Sure, I will check and fix it. I ran checkpatch, it didn't reported errors/warning related to that. > > > @@ -38,29 +38,32 @@ struct xintc_irq_chip { > > void __iomem *base; > > struct irq_domain *root_domain; > > u32 intr_mask; > > + struct irq_chip *intc_dev; > > + u32 nr_irq; > > }; > > > > -static struct xintc_irq_chip *xintc_irqc; > > +static struct xintc_irq_chip *primary_intc; > > > > -static void xintc_write(int reg, u32 data) > > +static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 > > +data) > > { > > if (static_branch_unlikely(&xintc_is_be)) > > - iowrite32be(data, xintc_irqc->base + reg); > > + iowrite32be(data, irqc->base + reg); > > else > > - iowrite32(data, xintc_irqc->base + reg); > > + iowrite32(data, irqc->base + reg); > > } > > > > -static unsigned int xintc_read(int reg) > > +static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) > > { > > if (static_branch_unlikely(&xintc_is_be)) > > - return ioread32be(xintc_irqc->base + reg); > > + return ioread32be(irqc->base + reg); > > else > > - return ioread32(xintc_irqc->base + reg); > > + return ioread32(irqc->base + reg); > > } > > > > static void intc_enable_or_unmask(struct irq_data *d) { > > - unsigned long mask = 1 << d->hwirq; > > + unsigned long mask = BIT(d->hwirq); > > + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); > > Please order your local variables in reverse fir tree order: > > struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); > unsigned long mask = BIT(d->hwirq); > > which is the preferred coding style in this subsystem and way simpler to > read. [Mubin]: I will fix all such instances in next version > > > static void intc_mask_ack(struct irq_data *d) { > > - unsigned long mask = 1 << d->hwirq; > > + unsigned long mask = BIT(d->hwirq); > > + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); > > Ditto. > > > pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); > > - xintc_write(CIE, mask); > > - xintc_write(IAR, mask); > > + xintc_write(irqc, CIE, mask); > > + xintc_write(irqc, IAR, mask); > > } > > +static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc) > > +{ > > + u32 hwirq; > > + unsigned int irq = 0; > > Same. > > > + hwirq = xintc_read(irqc, IVR); > > + if (hwirq != -1U) > > + irq = irq_find_mapping(irqc->root_domain, hwirq); > > + > > + pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); > > Are these pr_debugs all over the please really required? I can understand > that you use them for development, but are they useful once the stuff > works? [Mubin] They might be useful to debug interrupt issues. Do you want me to remove them? > > > + return irq; > > +} > > + > > unsigned int xintc_get_irq(void) > > { > > - unsigned int hwirq, irq = -1; > > + u32 hwirq; > > + unsigned int irq = -1; > > See above. > > > - hwirq = xintc_read(IVR); > > + hwirq = xintc_read(primary_intc, IVR); > > if (hwirq != -1U) > > - irq = irq_find_mapping(xintc_irqc->root_domain, hwirq); > > + irq = irq_find_mapping(primary_intc->root_domain, hwirq); > > > > pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); > > > > @@ -138,12 +164,14 @@ static const struct irq_domain_ops > > xintc_irq_domain_ops = { static void xil_intc_irq_handler(struct > > irq_desc *desc) { > > struct irq_chip *chip = irq_desc_get_chip(desc); > > + struct xintc_irq_chip *irqc = > > + irq_data_get_irq_handler_data(&desc->irq_data); > > Please avoid these ugly line breaks and put the initialization of the variable in > to the code below the declaration. [Mubin]: Will do in next version > > > /* Turn on the Master Enable. */ > > - xintc_write(MER, MER_HIE | MER_ME); > > - if (!(xintc_read(MER) & (MER_HIE | MER_ME))) { > > + xintc_write(irqc, MER, MER_HIE | MER_ME); > > + if (!(xintc_read(irqc, MER) & (MER_HIE | MER_ME))) { > > static_branch_enable(&xintc_is_be); > > I see it's existing logic, but this lacks a comment how it's determined that > xintc is big endian. Looks like some weird "write works?" > probing. Why? > > > + xintc_write(irqc, MER, MER_HIE | MER_ME); > > So this writes MER_HIE | MER_ME into MER > > > + if (!(xintc_read(irqc, MER) & (MER_HIE | MER_ME))) { > > but this checks just whether ONE of the bits is set. Shouldn't it check for MER > == (MER_HIE | MER_ME), i.e. read back what was written? [Mubin]: Agreed, will fix it in v4. Thanks, Mubin > > Thanks, > > tglx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel