* [PATCH v6 0/5] add imx8dxl evk support
@ 2022-08-22 17:52 Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 1/5] dt-bindings: firmware: add missing resource IDs for imx8dxl Shenwei Wang
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
The series of patches is to add the imx8dxl soc and its evk board
support.
changes in V6:
- The V6 changes mainly respond to the comments from Shawn
- Separate the V5 patch into SoC and Board commits
- Remove the unnecessary properties of "max-frequency"
in usdhc2 node
- Remove the unnecessary properties of "clk_csr" in eqos node
- Fix several coding style problems
changes in V5:
- change the "scu" node name to "system-controller"
- fix the typo in the comments for imx8dxl evk board
changes in V4:
- move i2c/mmc/serial aliases from soc to board
- correct the node names to follow the generic names recommendation
- remove some unused nodes in the evk board dts
changes in V3:
- re-order the commit sequence according to Krzysztof's feedback
- correct the syntax and styple problems pointed by Krzysztof
(Thank you for the detailed review, Krzysztof!)
- remove the unused nodes in imx8dxl-evk.dts
- dt_binding_check passed
Changes in V2:
- removed the edma2 device node because the edma v3 driver hasn't been
upstreamed yet.
- removed the imx8dxl_cm4 alias to fix the compile error.
- removed the extra blank lines at EOF.
- dt_binding_check passed.
Shenwei Wang (5):
dt-bindings: firmware: add missing resource IDs for imx8dxl
dt-bindings: arm: imx: update fsl.yaml for imx8dxl
arm64: dts: imx8: add a node label to ddr-pmu
arm64: dts: freescale: add i.MX8DXL SoC support
arm64: dts: freescale: add support for i.MX8DXL EVK board
.../devicetree/bindings/arm/fsl.yaml | 6 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 426 ++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 52 +++
.../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 142 ++++++
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 9 +
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 74 +++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 238 ++++++++++
include/dt-bindings/firmware/imx/rsrc.h | 7 +
10 files changed, 956 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
--
2.25.1
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v6 1/5] dt-bindings: firmware: add missing resource IDs for imx8dxl
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
@ 2022-08-22 17:52 ` Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 2/5] dt-bindings: arm: imx: update fsl.yaml " Shenwei Wang
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang,
Rob Herring
Add the missing resource IDs for imx8dxl.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
include/dt-bindings/firmware/imx/rsrc.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h
index 43885056557c..1675de05ad33 100644
--- a/include/dt-bindings/firmware/imx/rsrc.h
+++ b/include/dt-bindings/firmware/imx/rsrc.h
@@ -37,10 +37,14 @@
#define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22
#define IMX_SC_R_PERF 23
+#define IMX_SC_R_USB_1_PHY 24
#define IMX_SC_R_DC_0_WARP 25
+#define IMX_SC_R_V2X_MU_0 26
+#define IMX_SC_R_V2X_MU_1 27
#define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30
+#define IMX_SC_R_V2X_MU_2 31
#define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34
@@ -49,7 +53,10 @@
#define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39
+#define IMX_SC_R_V2X_MU_3 40
+#define IMX_SC_R_V2X_MU_4 41
#define IMX_SC_R_DC_1_WARP 42
+#define IMX_SC_R_SECVIO 44
#define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47
--
2.25.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 2/5] dt-bindings: arm: imx: update fsl.yaml for imx8dxl
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 1/5] dt-bindings: firmware: add missing resource IDs for imx8dxl Shenwei Wang
@ 2022-08-22 17:52 ` Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 3/5] arm64: dts: imx8: add a node label to ddr-pmu Shenwei Wang
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang,
Krzysztof Kozlowski
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7431579ab0e8..4f4c9c0a1315 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1034,6 +1034,12 @@ properties:
- toradex,colibri-imx8x # Colibri iMX8X Modules
- const: fsl,imx8qxp
+ - description: i.MX8DXL based Boards
+ items:
+ - enum:
+ - fsl,imx8dxl-evk # i.MX8DXL EVK Board
+ - const: fsl,imx8dxl
+
- description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
items:
- enum:
--
2.25.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 3/5] arm64: dts: imx8: add a node label to ddr-pmu
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 1/5] dt-bindings: firmware: add missing resource IDs for imx8dxl Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 2/5] dt-bindings: arm: imx: update fsl.yaml " Shenwei Wang
@ 2022-08-22 17:52 ` Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 4/5] arm64: dts: freescale: add i.MX8DXL SoC support Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board Shenwei Wang
4 siblings, 0 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang
The ddr-pmu on i.mx8dxl has a different interrupt number.
Add a node label to ddr-pmu so that it could be referred
and changed in i.mx8dxl dts.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
index 8b5cad4e2700..7d5183c6c5be 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
@@ -10,7 +10,7 @@ ddr_subsys: bus@5c000000 {
#size-cells = <1>;
ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
- ddr-pmu@5c020000 {
+ ddr_pmu0: ddr-pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
--
2.25.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 4/5] arm64: dts: freescale: add i.MX8DXL SoC support
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
` (2 preceding siblings ...)
2022-08-22 17:52 ` [PATCH v6 3/5] arm64: dts: imx8: add a node label to ddr-pmu Shenwei Wang
@ 2022-08-22 17:52 ` Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board Shenwei Wang
4 siblings, 0 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
This patch adds the basic support for i.MX8DXL SoC.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 52 ++++
.../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 142 +++++++++++
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 9 +
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 74 ++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 238 ++++++++++++++++++
5 files changed, 515 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..795d1d472fae
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020, 2022 NXP
+ */
+
+&audio_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&i2c0 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
new file mode 100644
index 000000000000..69c4849f2132
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020, 2022 NXP
+ */
+
+/delete-node/ &enet1_lpcg;
+/delete-node/ &fec2;
+
+&conn_subsys {
+ conn_enet0_root_clk: clock-conn-enet0-root {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "conn_enet0_root_clk";
+ };
+
+ eqos: ethernet@5b050000 {
+ compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x5b050000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
+ <&eqos_lpcg IMX_LPCG_CLK_6>,
+ <&eqos_lpcg IMX_LPCG_CLK_0>,
+ <&eqos_lpcg IMX_LPCG_CLK_5>,
+ <&eqos_lpcg IMX_LPCG_CLK_2>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <125000000>;
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@5b0e0000 {
+ compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
+ reg = <0x5b0e0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ /*
+ * usbotg1 and usbotg2 share one clcok.
+ * scu firmware disables the access to the clock and keeps
+ * it always on in case other core (M4) uses one of these.
+ */
+ clocks = <&clk_dummy>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ #stream-id-cells = <1>;
+ power-domains = <&pd IMX_SC_R_USB_1>;
+ status = "disabled";
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+ };
+
+ usbmisc2: usbmisc@5b0e0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7ulp-usbmisc";
+ reg = <0x5b0e0200 0x200>;
+ };
+
+ usbphy2: usbphy@0x5b110000 {
+ compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
+ reg = <0x5b110000 0x1000>;
+ clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
+ power-domains = <&pd IMX_SC_R_USB_1_PHY>;
+ status = "disabled";
+ };
+
+ eqos_lpcg: clock-controller@5b240000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "eqos_ptp",
+ "eqos_mem_clk",
+ "eqos_aclk",
+ "eqos_clk",
+ "eqos_csr_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
+
+ usb2_2_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+ clock-indices = <IMX_LPCG_CLK_7>;
+ clocks = <&conn_ipg_clk>;
+ clock-output-names = "usboh3_2_phy_ipg_clk";
+ power-domains = <&pd IMX_SC_R_USB_1_PHY>;
+ };
+
+};
+
+&enet0_lpcg {
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
+};
+
+&fec1 {
+ compatible = "fsl,imx8qm-fec";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <125000000>;
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc3 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..550f513708d8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+&ddr_pmu0 {
+ compatible = "fsl,imx8-ddr-pmu";
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..815bd987b09b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020, 2022 NXP
+ */
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu5 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
new file mode 100644
index 000000000000..5ddbda0b4def
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020, 2022 NXP
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &eqos;
+ gpio0 = &lsio_gpio0;
+ gpio1 = &lsio_gpio1;
+ gpio2 = &lsio_gpio2;
+ gpio3 = &lsio_gpio3;
+ gpio4 = &lsio_gpio4;
+ gpio5 = &lsio_gpio5;
+ gpio6 = &lsio_gpio6;
+ gpio7 = &lsio_gpio7;
+ mu1 = &lsio_mu1;
+ };
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* We have 1 clusters with 2 Cortex-A35 cores */
+ A35_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&a35_opp_table>;
+ };
+
+ A35_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&a35_opp_table>;
+ };
+
+ A35_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ a35_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_reserved: dsp@92400000 {
+ reg = <0 0x92400000 0 0x2000000>;
+ no-map;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ system-controller {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0",
+ "rx0",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 1 0
+ &lsio_mu1 3 3>;
+
+ pd: power-controller {
+ compatible = "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ wakeup-irq = <160 163 235 236 237 228 229 230 231 238
+ 239 240 166 169>;
+ };
+
+ clk: clock-controller {
+ compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ clocks = <&xtal32k &xtal24m>;
+ clock-names = "xtal_32KHz", "xtal_24Mhz";
+ };
+
+ iomuxc: pinctrl {
+ compatible = "fsl,imx8dxl-iomuxc";
+ };
+
+ ocotp: ocotp {
+ compatible = "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+
+ fec_mac1: mac@2c6 {
+ reg = <0x2c6 6>;
+ };
+ };
+
+ rtc: rtc {
+ compatible = "fsl,imx8qxp-sc-rtc";
+ };
+
+ sc_pwrkey: keys {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ watchdog {
+ compatible = "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ };
+
+ thermal_zones: thermal-zones {
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ /* The two values below cannot be changed by the board */
+ xtal32k: clock-xtal32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32KHz";
+ };
+
+ xtal24m: clock-xtal24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal_24MHz";
+ };
+
+ /* sorted in register address */
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+};
+
+#include "imx8dxl-ss-adma.dtsi"
+#include "imx8dxl-ss-conn.dtsi"
+#include "imx8dxl-ss-lsio.dtsi"
+#include "imx8dxl-ss-ddr.dtsi"
--
2.25.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
` (3 preceding siblings ...)
2022-08-22 17:52 ` [PATCH v6 4/5] arm64: dts: freescale: add i.MX8DXL SoC support Shenwei Wang
@ 2022-08-22 17:52 ` Shenwei Wang
2022-09-03 3:48 ` Shawn Guo
4 siblings, 1 reply; 14+ messages in thread
From: Shenwei Wang @ 2022-08-22 17:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan
Cc: devicetree, linux-arm-kernel, imx, NXP Linux Team, Shenwei Wang
This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL.
The patch has enabled the serial console, SD/EMMC interface, and
the eqos and fec ethernet network.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 427 ++++++++++++++++++
2 files changed, 428 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8bf7f7ecebaa..2741205efe84 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
new file mode 100644
index 000000000000..bc343d96f46e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019~2020, 2022 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxl.dtsi"
+
+/ {
+ model = "Freescale i.MX8DXL EVK";
+ compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+ aliases {
+ i2c2 = &i2c2;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart0;
+ };
+
+ chosen {
+ stdout-path = &lpuart0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * Memory reserved for optee usage. Please do not use.
+ * This will be automatically added to dtb if OP-TEE is installed.
+ * optee@96000000 {
+ * reg = <0 0x96000000 0 0x2000000>;
+ * no-map;
+ * };
+ */
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x14000000>;
+ alloc-ranges = <0 0x98000000 0 0x14000000>;
+ linux,cma-default;
+ };
+ };
+
+ mux3_en: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "mux3_en";
+ gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ reg_fec1_sel: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec1_supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ status = "disabled";
+ };
+
+ reg_fec1_io: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec1_io_supply";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ status = "disabled";
+ };
+
+ reg_usdhc2_vmmc: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <3480>;
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ nvmem-cells = <&fec_mac1>;
+ nvmem-cell-names = "mac-address";
+ snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
+ snps,reset-delays-us = <10 20 200000>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ eee-broken-1000t;
+ qca,disable-smarteee;
+ vddio-supply = <&vddio0>;
+
+ vddio0: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+/*
+ * fec1 shares the some PINs with usdhc2.
+ * by default usdhc2 is enabled in this dts.
+ * Please disable usdhc2 to enable fec1
+ */
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ rx-internal-delay-ps = <2000>;
+ nvmem-cells = <&fec_mac0>;
+ nvmem-cell-names = "mac-address";
+ phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <150>;
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ qca,disable-smarteee;
+ vddio-supply = <&vddio1>;
+
+ vddio1: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pca6416_1: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca6416_2: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9548_1: i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&lsio_gpio4 {
+ status = "okay";
+};
+
+&lsio_gpio5 {
+ status = "okay";
+};
+
+&thermal_zones {
+ pmic-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
+ IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
+ IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
+ >;
+ };
+
+ pinctrl_usbotg2: usbotg2grp {
+ fsl,pins = <
+ IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
+ IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
+ IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
+ IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
+ IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
+ IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
+ >;
+ };
+
+ pinctrl_lpspi3: lpspi3grp {
+ fsl,pins = <
+ IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
+ IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
+ IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
+ IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
+ >;
+ };
+
+ pinctrl_cm40_lpuart: cm40lpuartgrp {
+ fsl,pins = <
+ IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
+ IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
+ IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
+ IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-08-22 17:52 ` [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board Shenwei Wang
@ 2022-09-03 3:48 ` Shawn Guo
2022-09-06 13:15 ` [EXT] " Shenwei Wang
0 siblings, 1 reply; 14+ messages in thread
From: Shawn Guo @ 2022-09-03 3:48 UTC (permalink / raw)
To: Shenwei Wang
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, NXP Linux Team
On Mon, Aug 22, 2022 at 12:52:45PM -0500, Shenwei Wang wrote:
> This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL.
> The patch has enabled the serial console, SD/EMMC interface, and
> the eqos and fec ethernet network.
>
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 427 ++++++++++++++++++
> 2 files changed, 428 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 8bf7f7ecebaa..2741205efe84 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
>
> +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> new file mode 100644
> index 000000000000..bc343d96f46e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> @@ -0,0 +1,427 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019~2020, 2022 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8dxl.dtsi"
> +
> +/ {
> + model = "Freescale i.MX8DXL EVK";
> + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
> +
> + aliases {
> + i2c2 = &i2c2;
> + mmc0 = &usdhc1;
> + mmc1 = &usdhc2;
> + serial0 = &lpuart0;
> + };
> +
> + chosen {
> + stdout-path = &lpuart0;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x00000000 0x80000000 0 0x40000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /*
> + * Memory reserved for optee usage. Please do not use.
> + * This will be automatically added to dtb if OP-TEE is installed.
> + * optee@96000000 {
> + * reg = <0 0x96000000 0 0x2000000>;
> + * no-map;
> + * };
> + */
> +
> + /* global autoconfigured region for contiguous allocations */
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0 0x14000000>;
> + alloc-ranges = <0 0x98000000 0 0x14000000>;
> + linux,cma-default;
> + };
> + };
> +
> + mux3_en: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "mux3_en";
> + gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
> + regulator-always-on;
> + };
> +
> + reg_fec1_sel: regulator-1 {
> + compatible = "regulator-fixed";
> + regulator-name = "fec1_supply";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
Missing enable-active-high?
> + regulator-always-on;
> + status = "disabled";
> + };
> +
> + reg_fec1_io: regulator-2 {
> + compatible = "regulator-fixed";
> + regulator-name = "fec1_io_supply";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + status = "disabled";
> + };
> +
> + reg_usdhc2_vmmc: regulator-3 {
> + compatible = "regulator-fixed";
> + regulator-name = "SD1_SPWR";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + off-on-delay-us = <3480>;
> + };
> +};
> +
> +&eqos {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + nvmem-cells = <&fec_mac1>;
> + nvmem-cell-names = "mac-address";
> + snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
> + snps,reset-delays-us = <10 20 200000>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + eee-broken-1000t;
> + qca,disable-smarteee;
> + vddio-supply = <&vddio0>;
> +
> + vddio0: vddio-regulator {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> + };
> + };
> +};
> +
> +/*
> + * fec1 shares the some PINs with usdhc2.
> + * by default usdhc2 is enabled in this dts.
> + * Please disable usdhc2 to enable fec1
> + */
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-txid";
> + phy-handle = <ðphy1>;
> + fsl,magic-packet;
> + rx-internal-delay-ps = <2000>;
> + nvmem-cells = <&fec_mac0>;
> + nvmem-cell-names = "mac-address";
> + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <10>;
> + phy-reset-post-delay = <150>;
These are listed as deprecated optional properties in fsl,fec.yaml.
Shawn
> + status = "disabled";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + qca,disable-smarteee;
> + vddio-supply = <&vddio1>;
> +
> + vddio1: vddio-regulator {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + pca6416_1: gpio@20 {
> + compatible = "ti,tca6416";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + pca6416_2: gpio@21 {
> + compatible = "ti,tca6416";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + pca9548_1: i2c-mux@70 {
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x70>;
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0>;
> +
> + max7322: gpio@68 {
> + compatible = "maxim,max7322";
> + reg = <0x68>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> + };
> +
> + i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> + };
> +
> + i2c@5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x5>;
> + };
> +
> + i2c@6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x6>;
> + };
> + };
> +};
> +
> +&lpuart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart0>;
> + status = "okay";
> +};
> +
> +&lsio_gpio4 {
> + status = "okay";
> +};
> +
> +&lsio_gpio5 {
> + status = "okay";
> +};
> +
> +&thermal_zones {
> + pmic-thermal0 {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
> +
> + trips {
> + pmic_alert0: trip0 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + pmic_crit0: trip1 {
> + temperature = <125000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&pmic_alert0>;
> + cooling-device =
> + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + bus-width = <8>;
> + no-sd;
> + no-sdio;
> + non-removable;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + bus-width = <4>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
> + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
> + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
> + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1grp {
> + fsl,pins = <
> + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
> + >;
> + };
> +
> + pinctrl_usbotg2: usbotg2grp {
> + fsl,pins = <
> + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
> + >;
> + };
> +
> + pinctrl_eqos: eqosgrp {
> + fsl,pins = <
> + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
> + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
> + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
> + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
> + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
> + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
> + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
> + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
> + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
> + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
> + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
> + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
> + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
> + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
> + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
> + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
> + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
> + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
> + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
> + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
> + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
> + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
> + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
> + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
> + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
> + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
> + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
> + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
> + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
> + >;
> + };
> +
> + pinctrl_lpspi3: lpspi3grp {
> + fsl,pins = <
> + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
> + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
> + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
> + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
> + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
> + >;
> + };
> +
> + pinctrl_cm40_lpuart: cm40lpuartgrp {
> + fsl,pins = <
> + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
> + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
> + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
> + >;
> + };
> +
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
> + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
> + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
> + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
> + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
> + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
> + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
> + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
> + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
> + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
> + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
> + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
> + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
> + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
> + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
> + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
> + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
> + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
> + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
> + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
> + >;
> + };
> +};
> --
> 2.25.1
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-03 3:48 ` Shawn Guo
@ 2022-09-06 13:15 ` Shenwei Wang
2022-09-12 8:16 ` Shawn Guo
0 siblings, 1 reply; 14+ messages in thread
From: Shenwei Wang @ 2022-09-06 13:15 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Friday, September 2, 2022 10:48 PM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; Peng Fan
> <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; imx@lists.linux.dev; dl-linux-imx <linux-
> imx@nxp.com>
> Subject: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for
> i.MX8DXL EVK board
>
> > + regulator-always-on;
> > + };
> > +
> > + reg_fec1_sel: regulator-1 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fec1_supply";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
>
> Missing enable-active-high?
No. Enabling this regulator to select the fec1 interface instead of usdhc2. Pulling this GPIO pin to low is to use FEC1 interface.
>
> > + regulator-always-on;
> > + status = "disabled";
> > + };
> > +
> > + reg_fec1_io: regulator-2 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fec1_io_supply";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
...
> > + fsl,magic-packet;
> > + rx-internal-delay-ps = <2000>;
> > + nvmem-cells = <&fec_mac0>;
> > + nvmem-cell-names = "mac-address";
> > + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
> > + phy-reset-duration = <10>;
> > + phy-reset-post-delay = <150>;
>
> These are listed as deprecated optional properties in fsl,fec.yaml.
Will move the reset properties to phy node according to the new rule.
Thanks,
Shenwei
>
> Shawn
>
> > + status = "disabled";
> > +
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + ethphy1: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + qca,disable-smarteee;
> > + vddio-supply = <&vddio1>;
> > +
> > + vddio1: vddio-regulator {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&i2c2 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c2>;
> > + status = "okay";
> > +
> > + pca6416_1: gpio@20 {
> > + compatible = "ti,tca6416";
> > + reg = <0x20>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
> > + pca6416_2: gpio@21 {
> > + compatible = "ti,tca6416";
> > + reg = <0x21>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
> > + pca9548_1: i2c-mux@70 {
> > + compatible = "nxp,pca9548";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x70>;
> > +
> > + i2c@0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0>;
> > +
> > + max7322: gpio@68 {
> > + compatible = "maxim,max7322";
> > + reg = <0x68>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + i2c@4 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x4>;
> > + };
> > +
> > + i2c@5 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x5>;
> > + };
> > +
> > + i2c@6 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x6>;
> > + };
> > + };
> > +};
> > +
> > +&lpuart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_lpuart0>;
> > + status = "okay";
> > +};
> > +
> > +&lsio_gpio4 {
> > + status = "okay";
> > +};
> > +
> > +&lsio_gpio5 {
> > + status = "okay";
> > +};
> > +
> > +&thermal_zones {
> > + pmic-thermal0 {
> > + polling-delay-passive = <250>;
> > + polling-delay = <2000>;
> > + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
> > +
> > + trips {
> > + pmic_alert0: trip0 {
> > + temperature = <110000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + pmic_crit0: trip1 {
> > + temperature = <125000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&pmic_alert0>;
> > + cooling-device =
> > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&usdhc1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc1>;
> > + bus-width = <8>;
> > + no-sd;
> > + no-sdio;
> > + non-removable;
> > + status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > + bus-width = <4>;
> > + vmmc-supply = <®_usdhc2_vmmc>;
> > + cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
> > + wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
> > + status = "okay";
> > +};
> > +
> > +&iomuxc {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_hog>;
> > +
> > + pinctrl_hog: hoggrp {
> > + fsl,pins = <
> > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD
> 0x000514a0
> > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD
> 0x000014a0
> > + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1
> 0x0600004c
> > + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN
> 0x0600004c
> > + >;
> > + };
> > +
> > + pinctrl_usbotg1: usbotg1grp {
> > + fsl,pins = <
> > + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR
> 0x00000021
> > + >;
> > + };
> > +
> > + pinctrl_usbotg2: usbotg2grp {
> > + fsl,pins = <
> > + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR
> 0x00000021
> > + >;
> > + };
> > +
> > + pinctrl_eqos: eqosgrp {
> > + fsl,pins = <
> > + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC
> 0x06000020
> > + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3
> 0x06000020
> > + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL
> 0x06000020
> > + >;
> > + };
> > +
> > + pinctrl_fec1: fec1grp {
> > + fsl,pins = <
> > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD
> 0x000014a0
> > + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD
> 0x000014a0
> > + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC
> 0x06000020
> > + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO
> 0x06000020
> > + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
> 0x00000060
> > + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
> 0x00000060
> > + >;
> > + };
> > +
> > + pinctrl_lpspi3: lpspi3grp {
> > + fsl,pins = <
> > + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
> > + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
> > + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
> > + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
> > + >;
> > + };
> > +
> > + pinctrl_i2c2: i2c2grp {
> > + fsl,pins = <
> > + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
> > + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
> > + >;
> > + };
> > +
> > + pinctrl_cm40_lpuart: cm40lpuartgrp {
> > + fsl,pins = <
> > + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
> > + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
> > + >;
> > + };
> > +
> > + pinctrl_i2c3: i2c3grp {
> > + fsl,pins = <
> > + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
> > + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
> > + >;
> > + };
> > +
> > + pinctrl_lpuart0: lpuart0grp {
> > + fsl,pins = <
> > + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
> > + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
> > + >;
> > + };
> > +
> > + pinctrl_usdhc1: usdhc1grp {
> > + fsl,pins = <
> > + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
> > + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
> > + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
> > + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
> > + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
> > + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
> > + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
> > + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
> > + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
> > + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
> > + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE
> 0x00000041
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> > + fsl,pins = <
> > + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30
> 0x00000040 /* RESET_B */
> > + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00
> 0x00000021 /* WP */
> > + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01
> 0x00000021 /* CD */
> > + >;
> > + };
> > +
> > + pinctrl_usdhc2: usdhc2grp {
> > + fsl,pins = <
> > + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK
> 0x06000041
> > + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD
> 0x00000021
> > + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0
> 0x00000021
> > + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1
> 0x00000021
> > + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2
> 0x00000021
> > + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3
> 0x00000021
> > + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT
> 0x00000021
> > + >;
> > + };
> > +};
> > --
> > 2.25.1
> >
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-06 13:15 ` [EXT] " Shenwei Wang
@ 2022-09-12 8:16 ` Shawn Guo
2022-09-12 14:35 ` Shenwei Wang
0 siblings, 1 reply; 14+ messages in thread
From: Shawn Guo @ 2022-09-12 8:16 UTC (permalink / raw)
To: Shenwei Wang
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
On Tue, Sep 06, 2022 at 01:15:37PM +0000, Shenwei Wang wrote:
>
>
> > -----Original Message-----
> > From: Shawn Guo <shawnguo@kernel.org>
> > Sent: Friday, September 2, 2022 10:48 PM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; Peng Fan
> > <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; imx@lists.linux.dev; dl-linux-imx <linux-
> > imx@nxp.com>
> > Subject: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for
> > i.MX8DXL EVK board
> >
> > > + regulator-always-on;
> > > + };
> > > +
> > > + reg_fec1_sel: regulator-1 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "fec1_supply";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
> >
> > Missing enable-active-high?
>
> No. Enabling this regulator to select the fec1 interface instead of usdhc2. Pulling this GPIO pin to low is to use FEC1 interface.
Then the polarity cell should be GPIO_ACTIVE_LOW rather than
GPIO_ACTIVE_HIGH?
Shawn
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^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-12 8:16 ` Shawn Guo
@ 2022-09-12 14:35 ` Shenwei Wang
2022-09-13 2:07 ` Shawn Guo
2022-09-13 8:44 ` Krzysztof Kozlowski
0 siblings, 2 replies; 14+ messages in thread
From: Shenwei Wang @ 2022-09-12 14:35 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, September 12, 2022 3:17 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; Peng Fan
> <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; imx@lists.linux.dev; dl-linux-imx <linux-
> imx@nxp.com>
> > > > +
> > > > + reg_fec1_sel: regulator-1 {
> > > > + compatible = "regulator-fixed";
> > > > + regulator-name = "fec1_supply";
> > > > + regulator-min-microvolt = <3300000>;
> > > > + regulator-max-microvolt = <3300000>;
> > > > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
> > >
> > > Missing enable-active-high?
> >
> > No. Enabling this regulator to select the fec1 interface instead of usdhc2.
> Pulling this GPIO pin to low is to use FEC1 interface.
>
> Then the polarity cell should be GPIO_ACTIVE_LOW rather than
> GPIO_ACTIVE_HIGH?
>
That doesn't matter since any GPIO phandle flags are ignored in the node of "regulator-fixed". The final flag is only determined by the property of "enable-active-high". If there is a "enable-active-high", the GPIO line works as active high. If no such a property, it works as active low by default. Right?
Regards,
Shenwei
> Shawn
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-12 14:35 ` Shenwei Wang
@ 2022-09-13 2:07 ` Shawn Guo
2022-09-13 12:39 ` Shenwei Wang
2022-09-13 8:44 ` Krzysztof Kozlowski
1 sibling, 1 reply; 14+ messages in thread
From: Shawn Guo @ 2022-09-13 2:07 UTC (permalink / raw)
To: Shenwei Wang
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
On Mon, Sep 12, 2022 at 02:35:18PM +0000, Shenwei Wang wrote:
>
>
> > -----Original Message-----
> > From: Shawn Guo <shawnguo@kernel.org>
> > Sent: Monday, September 12, 2022 3:17 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; Peng Fan
> > <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; imx@lists.linux.dev; dl-linux-imx <linux-
> > imx@nxp.com>
> > > > > +
> > > > > + reg_fec1_sel: regulator-1 {
> > > > > + compatible = "regulator-fixed";
> > > > > + regulator-name = "fec1_supply";
> > > > > + regulator-min-microvolt = <3300000>;
> > > > > + regulator-max-microvolt = <3300000>;
> > > > > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
> > > >
> > > > Missing enable-active-high?
> > >
> > > No. Enabling this regulator to select the fec1 interface instead of usdhc2.
> > Pulling this GPIO pin to low is to use FEC1 interface.
> >
> > Then the polarity cell should be GPIO_ACTIVE_LOW rather than
> > GPIO_ACTIVE_HIGH?
> >
>
> That doesn't matter since any GPIO phandle flags are ignored in the node of "regulator-fixed". The final flag is only determined by the property of "enable-active-high". If there is a "enable-active-high", the GPIO line works as active high. If no such a property, it works as active low by default. Right?
>
Well, we are talking about the correctness of DT (hardware description),
not how kernel driver works with DT.
Shawn
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-12 14:35 ` Shenwei Wang
2022-09-13 2:07 ` Shawn Guo
@ 2022-09-13 8:44 ` Krzysztof Kozlowski
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-13 8:44 UTC (permalink / raw)
To: Shenwei Wang, Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
On 12/09/2022 16:35, Shenwei Wang wrote:
>>>>> + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
>>>>
>>>> Missing enable-active-high?
>>>
>>> No. Enabling this regulator to select the fec1 interface instead of usdhc2.
>> Pulling this GPIO pin to low is to use FEC1 interface.
>>
>> Then the polarity cell should be GPIO_ACTIVE_LOW rather than
>> GPIO_ACTIVE_HIGH?
>>
>
> That doesn't matter since any GPIO phandle flags are ignored in the node of "regulator-fixed". The final flag is only determined by the property of "enable-active-high". If there is a "enable-active-high", the GPIO line works as active high. If no such a property, it works as active low by default. Right?
No. Your flags must match hardware, even if bindings also expect
enable-active-high.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-13 2:07 ` Shawn Guo
@ 2022-09-13 12:39 ` Shenwei Wang
2022-09-13 13:53 ` Krzysztof Kozlowski
0 siblings, 1 reply; 14+ messages in thread
From: Shenwei Wang @ 2022-09-13 12:39 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, September 12, 2022 9:07 PM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer <s.hauer@pengutronix.de>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; Peng Fan
> <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; imx@lists.linux.dev; dl-linux-imx <linux-
> imx@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for
> i.MX8DXL EVK board
>
> Caution: EXT Email
>
> On Mon, Sep 12, 2022 at 02:35:18PM +0000, Shenwei Wang wrote:
> >
> >
> > > -----Original Message-----
> > > From: Shawn Guo <shawnguo@kernel.org>
> > > Sent: Monday, September 12, 2022 3:17 AM
> > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer
> > > <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> > > <kernel@pengutronix.de>; Peng Fan <peng.fan@nxp.com>;
> > > devicetree@vger.kernel.org; linux-arm- kernel@lists.infradead.org;
> > > imx@lists.linux.dev; dl-linux-imx <linux- imx@nxp.com>
> > > > > > +
> > > > > > + reg_fec1_sel: regulator-1 {
> > > > > > + compatible = "regulator-fixed";
> > > > > > + regulator-name = "fec1_supply";
> > > > > > + regulator-min-microvolt = <3300000>;
> > > > > > + regulator-max-microvolt = <3300000>;
> > > > > > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
> > > > >
> > > > > Missing enable-active-high?
> > > >
> > > > No. Enabling this regulator to select the fec1 interface instead of usdhc2.
> > > Pulling this GPIO pin to low is to use FEC1 interface.
> > >
> > > Then the polarity cell should be GPIO_ACTIVE_LOW rather than
> > > GPIO_ACTIVE_HIGH?
> > >
> >
> > That doesn't matter since any GPIO phandle flags are ignored in the node of
> "regulator-fixed". The final flag is only determined by the property of "enable-
> active-high". If there is a "enable-active-high", the GPIO line works as active
> high. If no such a property, it works as active low by default. Right?
> >
>
> Well, we are talking about the correctness of DT (hardware description), not
> how kernel driver works with DT.
>
So the correct syntax here is: if enable-active-high is used, the flag of gpio phandle should also be configured as "ACTIVE_HIGH". Otherwise, if no enable-active-high, the GPIO flag should be "ACTIVE_LOW". Is my understanding correct?
Regards,
Shenwei
> Shawn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [EXT] Re: [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board
2022-09-13 12:39 ` Shenwei Wang
@ 2022-09-13 13:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-13 13:53 UTC (permalink / raw)
To: Shenwei Wang, Shawn Guo
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Peng Fan, devicetree, linux-arm-kernel,
imx, dl-linux-imx
On 13/09/2022 14:39, Shenwei Wang wrote:
>>
>> Well, we are talking about the correctness of DT (hardware description), not
>> how kernel driver works with DT.
>>
>
> So the correct syntax here is: if enable-active-high is used, the flag of gpio phandle should also be configured as "ACTIVE_HIGH". Otherwise, if no enable-active-high, the GPIO flag should be "ACTIVE_LOW". Is my understanding correct?
Yes.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-09-13 13:54 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-22 17:52 [PATCH v6 0/5] add imx8dxl evk support Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 1/5] dt-bindings: firmware: add missing resource IDs for imx8dxl Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 2/5] dt-bindings: arm: imx: update fsl.yaml " Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 3/5] arm64: dts: imx8: add a node label to ddr-pmu Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 4/5] arm64: dts: freescale: add i.MX8DXL SoC support Shenwei Wang
2022-08-22 17:52 ` [PATCH v6 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board Shenwei Wang
2022-09-03 3:48 ` Shawn Guo
2022-09-06 13:15 ` [EXT] " Shenwei Wang
2022-09-12 8:16 ` Shawn Guo
2022-09-12 14:35 ` Shenwei Wang
2022-09-13 2:07 ` Shawn Guo
2022-09-13 12:39 ` Shenwei Wang
2022-09-13 13:53 ` Krzysztof Kozlowski
2022-09-13 8:44 ` Krzysztof Kozlowski
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