From: Linu Cherian <lcherian@marvell.com>
To: James Clark <james.clark@arm.com>,
"suzuki.poulose@arm.com" <suzuki.poulose@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"coresight@lists.linaro.org" <coresight@lists.linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzysztof.kozlowski+dt@linaro.org"
<krzysztof.kozlowski+dt@linaro.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Sunil Kovvuri Goutham <sgoutham@marvell.com>,
George Cherian <gcherian@marvell.com>,
Anil Kumar Reddy H <areddy3@marvell.com>,
"mike.leach@linaro.org" <mike.leach@linaro.org>,
"leo.yan@linaro.org" <leo.yan@linaro.org>
Subject: RE: [EXTERNAL] Re: [PATCH v7 2/7] coresight: tmc-etr: Add support to use reserved trace memory
Date: Sun, 14 Apr 2024 10:09:41 +0000 [thread overview]
Message-ID: <PH0PR18MB500263D63DD07EF1C28017C8CE0A2@PH0PR18MB5002.namprd18.prod.outlook.com> (raw)
In-Reply-To: <3c5c85d4-8657-4ee0-88fa-ee47dce4cc7c@arm.com>
Hi James,
> -----Original Message-----
> From: James Clark <james.clark@arm.com>
> Sent: Friday, April 12, 2024 3:27 PM
> To: Linu Cherian <lcherian@marvell.com>; suzuki.poulose@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux-
> kernel@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> devicetree@vger.kernel.org; Sunil Kovvuri Goutham
> <sgoutham@marvell.com>; George Cherian <gcherian@marvell.com>; Anil
> Kumar Reddy H <areddy3@marvell.com>; mike.leach@linaro.org;
> leo.yan@linaro.org
> Subject: [EXTERNAL] Re: [PATCH v7 2/7] coresight: tmc-etr: Add support to
> use reserved trace memory
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
>
>
> On 07/03/2024 03:36, Linu Cherian wrote:
> > Add support to use reserved memory for coresight ETR trace buffer.
> >
> > Introduce a new ETR buffer mode called ETR_MODE_RESRV, which becomes
> > available when ETR device tree node is supplied with a valid reserved
> > memory region.
> >
> > ETR_MODE_RESRV can be selected only by explicit user request.
> >
> > $ echo resrv
> >/sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred
> >
> > Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
> > Signed-off-by: Linu Cherian <lcherian@marvell.com>
> > ---
> > Changelog from v6:
> > * Removed redundant goto statements
> > * Setting of etr_buf->size to the reserved memory size is done
> > after successful dma map inside the alloc function
> > * Removed the special casing for ETR_MODE_RESRV
> > * Fixed the tab spacing in struct tmc_drvdata
> >
> > .../hwtracing/coresight/coresight-tmc-core.c | 47 +++++++++++
> > .../hwtracing/coresight/coresight-tmc-etr.c | 82 ++++++++++++++++++-
> > drivers/hwtracing/coresight/coresight-tmc.h | 27 ++++++
> > 3 files changed, 153 insertions(+), 3 deletions(-)
> >
>
> [...]
>
> > static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t
> > etr_buf_size) @@ -874,13 +947,10 @@ static struct etr_buf
> *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,
> > if (!etr_buf)
> > return ERR_PTR(-ENOMEM);
> >
> > - etr_buf->size = size;
> > -
>
> Hi Linu,
>
> Not sure if this was left in by mistake? It's not mentioned in the commit
> message and it doesn't seem to match the description.
>
Yeah, that change was by mistake. Sorry about that.
> Please make sure the current tests pass both with and without a reserved
> buffer defined in the DT. I get lots of failures with this patchset applied on
> N1SDP. ETF seems to work but ETR doesn't:
>
Ack.
> $ sudo perf test -vvv "arm coresight"
>
> Recording trace (only user mode) with path: CPU1 => tmc_etf0
> CoreSight path testing (CPU1 -> tmc_etf0): PASS
>
> Recording trace (only user mode) with path: CPU1 => tmc_etr0
> CoreSight path testing (CPU1 -> tmc_etr0): FAIL
> ...
>
> Dmesg:
> [ 1938.622091] coresight tmc_etr0: Unable to allocate ETR buffer
>
> > /* If there is user directive for buffer mode, try that first */
> > if (drvdata->etr_mode != ETR_MODE_AUTO)
> > rc = tmc_etr_mode_alloc_buf(drvdata->etr_mode, drvdata,
> > etr_buf, node, pages);
> > -
>
> Whitespace change.
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next prev parent reply other threads:[~2024-04-14 10:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-07 3:36 [PATCH v7 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-03-07 3:36 ` [PATCH v7 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2024-03-07 3:36 ` [PATCH v7 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2024-04-12 9:57 ` James Clark
2024-04-14 10:09 ` Linu Cherian [this message]
2024-03-07 3:36 ` [PATCH v7 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
2024-03-07 3:36 ` [PATCH v7 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
2024-03-07 3:36 ` [PATCH v7 5/7] coresight: tmc: Add support for reading crash data Linu Cherian
2024-04-12 10:05 ` James Clark
2024-04-15 4:01 ` [EXTERNAL] " Linu Cherian
2024-04-15 9:28 ` James Clark
2024-04-21 2:49 ` Linu Cherian
2024-04-22 8:18 ` James Clark
2024-04-25 2:07 ` [EXTERNAL] " Linu Cherian
2024-04-25 9:32 ` James Clark
2024-03-07 3:36 ` [PATCH v7 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
2024-03-07 3:36 ` [PATCH v7 7/7] coresight: config: Add preloaded configuration Linu Cherian
2024-04-09 0:10 ` [PATCH v7 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-04-09 9:28 ` James Clark
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