From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A87D7C433FE for ; Wed, 26 Oct 2022 12:08:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wFf5lvlSFfrUsksqO05qb5iAuNs5mlcYKvvUN9yasF8=; b=Dl/OUHdp0c0EUt DITi/CAy91swVxQvMsyCrkVC/5bMm/RO0P3Ao92VgOw5mF6EQNaCH0WoIndhUqmWYlx9OW6RzvT6A IaVkrDpEHNCS4oacbbz007YYiIrMQoFrJnDDxpGfHqhRxCGoruKUUENaylhNwcupWXVpjGRLY2PFm bJ8IYMGLOjDpWJmeePoh3LqhN6+lWX647nc+i+BdTLE4hLn0SdBuff/pqadrbaRqBXg9kQjlnii41 77hBfodtEZGXxMHGfjJuZ533zETBbzEQFJOJlBJwLCm7zMZMw7PBN7jX0u74APZmX08ArMCg4NCu9 hEGds6OSbZ1olk1GqC7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1onfBY-00989O-Ux; Wed, 26 Oct 2022 12:07:05 +0000 Received: from vps0.lunn.ch ([156.67.10.101]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1onfBW-00985q-9T for linux-arm-kernel@lists.infradead.org; Wed, 26 Oct 2022 12:07:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=B/Gu8lEakeE0xZHUuCf+CKOgyX/EB7IG70Xl2GMpx+4=; b=tVG/8D65+b6EPoGSurRmyoakPV k/z/kQVzFoO6BOAhXTAiYYKN12ad/IH+vJaD+fvSYYOFW81JmqxoRjYhDEiWPAK57JOK8HlPGn7wG qf0CYIasYqAaMpVTdPUIIRb1kYgLgpkbDzAelOz0d0KvV68XH3hIfLdsnRK65bU1BwL8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1onf9x-000cVd-SM; Wed, 26 Oct 2022 14:05:25 +0200 Date: Wed, 26 Oct 2022 14:05:25 +0200 From: Andrew Lunn To: Maxime Chevallier Cc: Sean Anderson , davem@davemloft.net, Rob Herring , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Jakub Kicinski , Eric Dumazet , Paolo Abeni , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: Re: [PATCH net-next v3 3/5] net: pcs: add new PCS driver for altera TSE PCS Message-ID: References: <20220901143543.416977-1-maxime.chevallier@bootlin.com> <20220901143543.416977-4-maxime.chevallier@bootlin.com> <68b3dfbf-9bab-2554-254e-bffd280ba97e@gmail.com> <20221026113711.2b740c7a@pc-8.home> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221026113711.2b740c7a@pc-8.home> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_050702_369253_BF3CEAC0 X-CRM114-Status: GOOD ( 12.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > > > + /* This PCS seems to require a soft reset to re-sync the > > > AN logic */ > > > + tse_pcs_reset(tse_pcs); > > > > This is kinda strange since c22 phys are supposed to reset the other > > registers to default values when BMCR_RESET is written. Good thing > > this is a PCS... > > Indeed. This soft reset will not affect the register configuration, it > will only reset all internal state machines. > > The datasheet actually recommends performing a reset after any > configuration change... The Marvell PHYs work like this. Many of its registers won't take effect until you do a soft reset. I think the thinking behind this is that changing many registers is disruptive to the link and slow. It takes over a second to perform auto-neg etc. So ideally you want to make all your register changes, and then trigger them into operation. And a soft reset is this trigger. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel