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[35.233.69.230]) by smtp.gmail.com with ESMTPSA id b19sm6002248wmj.22.2021.02.04.06.07.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 06:07:08 -0800 (PST) Date: Thu, 4 Feb 2021 14:07:04 +0000 From: Quentin Perret To: Will Deacon Subject: Re: [RFC PATCH v2 21/26] KVM: arm64: Refactor kvm_arm_setup_stage2() Message-ID: References: <20210108121524.656872-1-qperret@google.com> <20210108121524.656872-22-qperret@google.com> <20210203155354.GE18974@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210203155354.GE18974@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210204_090712_676863_A6EF5CD5 X-CRM114-Status: GOOD ( 31.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, kernel-team@android.com, Suzuki K Poulose , android-kvm@google.com, Catalin Marinas , Fuad Tabba , linux-kernel@vger.kernel.org, Rob Herring , James Morse , linux-arm-kernel@lists.infradead.org, Marc Zyngier , David Brazdil , Frank Rowand , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wednesday 03 Feb 2021 at 15:53:54 (+0000), Will Deacon wrote: > On Fri, Jan 08, 2021 at 12:15:19PM +0000, Quentin Perret wrote: > > In order to re-use some of the stage 2 setup at EL2, factor parts of > > kvm_arm_setup_stage2() out into static inline functions. > > > > No functional change intended. > > > > Signed-off-by: Quentin Perret > > --- > > arch/arm64/include/asm/kvm_mmu.h | 48 ++++++++++++++++++++++++++++++++ > > arch/arm64/kvm/reset.c | 42 +++------------------------- > > 2 files changed, 52 insertions(+), 38 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > > index 662f0415344e..83b4c5cf4768 100644 > > --- a/arch/arm64/include/asm/kvm_mmu.h > > +++ b/arch/arm64/include/asm/kvm_mmu.h > > @@ -280,6 +280,54 @@ static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa, > > return ret; > > } > > > > +static inline u64 kvm_get_parange(u64 mmfr0) > > +{ > > + u64 parange = cpuid_feature_extract_unsigned_field(mmfr0, > > + ID_AA64MMFR0_PARANGE_SHIFT); > > + if (parange > ID_AA64MMFR0_PARANGE_MAX) > > + parange = ID_AA64MMFR0_PARANGE_MAX; > > + > > + return parange; > > +} > > + > > +/* > > + * The VTCR value is common across all the physical CPUs on the system. > > + * We use system wide sanitised values to fill in different fields, > > + * except for Hardware Management of Access Flags. HA Flag is set > > + * unconditionally on all CPUs, as it is safe to run with or without > > + * the feature and the bit is RES0 on CPUs that don't support it. > > + */ > > +static inline u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift) > > +{ > > + u64 vtcr = VTCR_EL2_FLAGS; > > + u8 lvls; > > + > > + vtcr |= kvm_get_parange(mmfr0) << VTCR_EL2_PS_SHIFT; > > + vtcr |= VTCR_EL2_T0SZ(phys_shift); > > + /* > > + * Use a minimum 2 level page table to prevent splitting > > + * host PMD huge pages at stage2. > > + */ > > + lvls = stage2_pgtable_levels(phys_shift); > > + if (lvls < 2) > > + lvls = 2; > > + vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls); > > + > > + /* > > + * Enable the Hardware Access Flag management, unconditionally > > + * on all CPUs. The features is RES0 on CPUs without the support > > + * and must be ignored by the CPUs. > > + */ > > + vtcr |= VTCR_EL2_HA; > > + > > + /* Set the vmid bits */ > > + vtcr |= (get_vmid_bits(mmfr1) == 16) ? > > + VTCR_EL2_VS_16BIT : > > + VTCR_EL2_VS_8BIT; > > + > > + return vtcr; > > +} > > Although I think this is functionally fine, I think it's unusual to see > large "static inline" functions like this in shared header files. One > alternative approach would be to follow the example of > kernel/locking/qspinlock_paravirt.h, where the header is guarded in such a > way that is only ever included by kernel/locking/qspinlock.c and therefore > doesn't need the "inline" at all. That separation really helps, I think. Alternatively, I might be able to have an mmu.c file in the hyp/ folder, and to compile it for both the host kernel and the EL2 obj as we do for a few things already. Or maybe I'll just stick it in pgtable.c. Either way, it'll add a function call, but I can't really see that having any measurable impact, so we should be fine. Cheers, Quentin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel