[PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string

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* [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
@ 2021-04-23  3:33 Dong Aisheng
  2021-04-23  3:33 ` [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding Dong Aisheng
                   ` (6 more replies)
  0 siblings, 7 replies; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd,
	Dong Aisheng, devicetree

There is a typo in binding doc that the name of compatible string of
scu clock should be "fsl,xxx-clk" rather than "fsl,xxx-clock".
In reality, both example and dts using "fsl,xxx-clk", so fixing the doc
is enough.

Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index 395359dc94fd..3adf3f6f2beb 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -86,8 +86,8 @@ This binding uses the common clock binding[1].
 
 Required properties:
 - compatible:		Should be one of:
-			  "fsl,imx8qm-clock"
-			  "fsl,imx8qxp-clock"
+			  "fsl,imx8qm-clk"
+			  "fsl,imx8qxp-clk"
 			followed by "fsl,scu-clk"
 - #clock-cells:		Should be either
 			2: Contains the Resource and Clock ID value.
-- 
2.25.1


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* [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
@ 2021-04-23  3:33 ` Dong Aisheng
  2021-05-03 16:47   ` Rob Herring
  2021-04-23  3:33 ` [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support Dong Aisheng
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd,
	Dong Aisheng, devicetree

The legacy clock binding are not maintained anymore. It has only
a very preliminary supported clocks during initial upstream and
meaningless for users. So drop it from binding doc now.

Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index 3adf3f6f2beb..fd0061712443 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -89,10 +89,8 @@ Required properties:
 			  "fsl,imx8qm-clk"
 			  "fsl,imx8qxp-clk"
 			followed by "fsl,scu-clk"
-- #clock-cells:		Should be either
-			2: Contains the Resource and Clock ID value.
-			or
-			1: Contains the Clock ID value. (DEPRECATED)
+- #clock-cells:		Should be 2.
+			Contains the Resource and Clock ID value.
 - clocks:		List of clock specifiers, must contain an entry for
 			each required entry in clock-names
 - clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"
-- 
2.25.1


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* Re: [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
  2021-04-23  3:33 ` [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding Dong Aisheng
@ 2021-05-03 16:47   ` Rob Herring
  0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-05-03 16:47 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-imx, linux-arm-kernel, kernel, devicetree, linux-clk,
	dongas86, shawnguo, abel.vesa, sboyd

On Fri, 23 Apr 2021 11:33:30 +0800, Dong Aisheng wrote:
> The legacy clock binding are not maintained anymore. It has only
> a very preliminary supported clocks during initial upstream and
> meaningless for users. So drop it from binding doc now.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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* [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
  2021-04-23  3:33 ` [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding Dong Aisheng
@ 2021-04-23  3:33 ` Dong Aisheng
  2021-05-13 20:04   ` Abel Vesa
  2021-04-23  3:33 ` [PATCH 4/6] clk: imx: scu: add gpr clocks support Dong Aisheng
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd, Dong Aisheng

Legacy scu clock binding are not maintained anymore, it has a very
limited clocks supported during initial upstreaming and obviously
unusable by products. So it's meaningless to keep it in
kernel which worse the code readability.
Remove it to keep code much cleaner.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c          | 201 ++++++++++---------------
 drivers/clk/imx/clk-scu.h              |  15 +-
 include/dt-bindings/clock/imx8-clock.h | 128 ----------------
 3 files changed, 81 insertions(+), 263 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index fbf1170c09ed..d17b418ac577 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -14,7 +14,6 @@
 
 #include "clk-scu.h"
 
-#include <dt-bindings/clock/imx8-clock.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 
 static const char *dc0_sels[] = {
@@ -28,149 +27,103 @@ static const char *dc0_sels[] = {
 static int imx8qxp_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *ccm_node = pdev->dev.of_node;
-	struct clk_hw_onecell_data *clk_data;
-	struct clk_hw **clks;
-	u32 clk_cells;
-	int ret, i;
+	int ret;
 
 	ret = imx_clk_scu_init(ccm_node);
 	if (ret)
 		return ret;
 
-	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
-				IMX_SCU_CLK_END), GFP_KERNEL);
-	if (!clk_data)
-		return -ENOMEM;
-
-	if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
-		return -EINVAL;
-
-	clk_data->num = IMX_SCU_CLK_END;
-	clks = clk_data->hws;
-
-	/* Fixed clocks */
-	clks[IMX_CLK_DUMMY]		= clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
-	clks[IMX_ADMA_IPG_CLK_ROOT] 	= clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
-	clks[IMX_CONN_AXI_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
-	clks[IMX_CONN_AHB_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
-	clks[IMX_CONN_IPG_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
-	clks[IMX_DC_AXI_EXT_CLK]	= clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
-	clks[IMX_DC_AXI_INT_CLK]	= clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
-	clks[IMX_DC_CFG_CLK]		= clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
-	clks[IMX_MIPI_IPG_CLK]		= clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
-	clks[IMX_IMG_AXI_CLK]		= clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
-	clks[IMX_IMG_IPG_CLK]		= clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
-	clks[IMX_IMG_PXL_CLK]		= clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
-	clks[IMX_HSIO_AXI_CLK]		= clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
-	clks[IMX_HSIO_PER_CLK]		= clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
-	clks[IMX_LSIO_MEM_CLK]		= clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
-	clks[IMX_LSIO_BUS_CLK]		= clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
-
 	/* ARM core */
-	clks[IMX_A35_CLK]		= imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
+	imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
 
 	/* LSIO SS */
-	clks[IMX_LSIO_PWM0_CLK]		= imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM1_CLK]		= imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM2_CLK]		= imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM3_CLK]		= imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM4_CLK]		= imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM5_CLK]		= imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM6_CLK]		= imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_PWM7_CLK]		= imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_GPT0_CLK]		= imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_GPT1_CLK]		= imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_GPT2_CLK]		= imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_GPT3_CLK]		= imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_GPT4_CLK]		= imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_FSPI0_CLK]	= imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_LSIO_FSPI1_CLK]	= imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
+	imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
 
 	/* ADMA SS */
-	clks[IMX_ADMA_UART0_CLK]	= imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_UART1_CLK]	= imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_UART2_CLK]	= imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_UART3_CLK]	= imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_SPI0_CLK]		= imx_clk_scu("spi0_clk",  IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_SPI1_CLK]		= imx_clk_scu("spi1_clk",  IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_SPI2_CLK]		= imx_clk_scu("spi2_clk",  IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_SPI3_CLK]		= imx_clk_scu("spi3_clk",  IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_CAN0_CLK]		= imx_clk_scu("can0_clk",  IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_I2C0_CLK]		= imx_clk_scu("i2c0_clk",  IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_I2C1_CLK]		= imx_clk_scu("i2c1_clk",  IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_I2C2_CLK]		= imx_clk_scu("i2c2_clk",  IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_I2C3_CLK]		= imx_clk_scu("i2c3_clk",  IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_FTM0_CLK]		= imx_clk_scu("ftm0_clk",  IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_FTM1_CLK]		= imx_clk_scu("ftm1_clk",  IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_ADC0_CLK]		= imx_clk_scu("adc0_clk",  IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_PWM_CLK]		= imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_ADMA_LCD_CLK]		= imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
+	imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("spi0_clk",  IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("spi1_clk",  IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("spi2_clk",  IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("spi3_clk",  IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("can0_clk",  IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("i2c0_clk",  IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("i2c1_clk",  IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("i2c2_clk",  IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("i2c3_clk",  IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("ftm0_clk",  IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("ftm1_clk",  IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("adc0_clk",  IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
 
 	/* Connectivity */
-	clks[IMX_CONN_SDHC0_CLK]	= imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_SDHC1_CLK]	= imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_SDHC2_CLK]	= imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_ENET0_ROOT_CLK]	= imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_ENET0_BYPASS_CLK]	= imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
-	clks[IMX_CONN_ENET0_RGMII_CLK]	= imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
-	clks[IMX_CONN_ENET1_ROOT_CLK]	= imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_ENET1_BYPASS_CLK]	= imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
-	clks[IMX_CONN_ENET1_RGMII_CLK]	= imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
-	clks[IMX_CONN_GPMI_BCH_IO_CLK]	= imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
-	clks[IMX_CONN_GPMI_BCH_CLK]	= imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_USB2_ACLK]	= imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CONN_USB2_BUS_CLK]	= imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
-	clks[IMX_CONN_USB2_LPM_CLK]	= imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
+	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
+	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
+	imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
 
 	/* Display controller SS */
-	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
-	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
-	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
-	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
-	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
-	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
+	imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
+	imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
+	imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
 
 	/* MIPI-LVDS SS */
-	clks[IMX_MIPI0_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI0_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
-	clks[IMX_MIPI0_LVDS_PHY_CLK]	= imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
-	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI0_I2C1_CLK]	= imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI0_PWM0_CLK]	= imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_MIPI1_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI1_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
-	clks[IMX_MIPI1_LVDS_PHY_CLK]	= imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
-	clks[IMX_MIPI1_I2C0_CLK]	= imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI1_I2C1_CLK]	= imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
-	clks[IMX_MIPI1_PWM0_CLK]	= imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
+	imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
+	imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
+	imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
 
 	/* MIPI CSI SS */
-	clks[IMX_CSI0_CORE_CLK]		= imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CSI0_ESC_CLK]		= imx_clk_scu("mipi_csi0_esc_clk",  IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
-	clks[IMX_CSI0_I2C0_CLK]		= imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_CSI0_PWM0_CLK]		= imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
+	imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("mipi_csi0_esc_clk",  IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
+	imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
 
 	/* GPU SS */
-	clks[IMX_GPU0_CORE_CLK]		= imx_clk_scu("gpu_core0_clk",	 IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
-	clks[IMX_GPU0_SHADER_CLK]	= imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
-
-	for (i = 0; i < clk_data->num; i++) {
-		if (IS_ERR(clks[i]))
-			pr_warn("i.MX clk %u: register failed with %ld\n",
-				i, PTR_ERR(clks[i]));
-	}
-
-	if (clk_cells == 2) {
-		ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
-		if (ret)
-			imx_clk_scu_unregister();
-	} else {
-		/*
-		 * legacy binding code path doesn't unregister here because
-		 * it will be removed later.
-		 */
-		ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
-	}
+	imx_clk_scu("gpu_core0_clk",	 IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
+
+	ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
+	if (ret)
+		imx_clk_scu_unregister();
 
 	return ret;
 }
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index e8352164923e..a6c6d3103e94 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -32,22 +32,15 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
 
 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
-					 u8 clk_type, u8 clk_cells)
+					 u8 clk_type)
 {
-	if (clk_cells == 2)
-		return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
-	else
-		return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type);
+	return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
 }
 
 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
-					  int num_parents, u32 rsrc_id, u8 clk_type,
-					  u8 clk_cells)
+					  int num_parents, u32 rsrc_id, u8 clk_type)
 {
-	if (clk_cells == 2)
-		return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
-	else
-		return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type);
+	return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
 }
 
 static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 82b1fc8d1ee0..2e60ce4d2622 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -7,134 +7,6 @@
 #ifndef __DT_BINDINGS_CLOCK_IMX_H
 #define __DT_BINDINGS_CLOCK_IMX_H
 
-/* SCU Clocks */
-
-#define IMX_CLK_DUMMY				0
-
-/* CPU */
-#define IMX_A35_CLK					1
-
-/* LSIO SS */
-#define IMX_LSIO_MEM_CLK				2
-#define IMX_LSIO_BUS_CLK				3
-#define IMX_LSIO_PWM0_CLK				10
-#define IMX_LSIO_PWM1_CLK				11
-#define IMX_LSIO_PWM2_CLK				12
-#define IMX_LSIO_PWM3_CLK				13
-#define IMX_LSIO_PWM4_CLK				14
-#define IMX_LSIO_PWM5_CLK				15
-#define IMX_LSIO_PWM6_CLK				16
-#define IMX_LSIO_PWM7_CLK				17
-#define IMX_LSIO_GPT0_CLK				18
-#define IMX_LSIO_GPT1_CLK				19
-#define IMX_LSIO_GPT2_CLK				20
-#define IMX_LSIO_GPT3_CLK				21
-#define IMX_LSIO_GPT4_CLK				22
-#define IMX_LSIO_FSPI0_CLK				23
-#define IMX_LSIO_FSPI1_CLK				24
-
-/* Connectivity SS */
-#define IMX_CONN_AXI_CLK_ROOT				30
-#define IMX_CONN_AHB_CLK_ROOT				31
-#define IMX_CONN_IPG_CLK_ROOT				32
-#define IMX_CONN_SDHC0_CLK				40
-#define IMX_CONN_SDHC1_CLK				41
-#define IMX_CONN_SDHC2_CLK				42
-#define IMX_CONN_ENET0_ROOT_CLK				43
-#define IMX_CONN_ENET0_BYPASS_CLK			44
-#define IMX_CONN_ENET0_RGMII_CLK			45
-#define IMX_CONN_ENET1_ROOT_CLK				46
-#define IMX_CONN_ENET1_BYPASS_CLK			47
-#define IMX_CONN_ENET1_RGMII_CLK			48
-#define IMX_CONN_GPMI_BCH_IO_CLK			49
-#define IMX_CONN_GPMI_BCH_CLK				50
-#define IMX_CONN_USB2_ACLK				51
-#define IMX_CONN_USB2_BUS_CLK				52
-#define IMX_CONN_USB2_LPM_CLK				53
-
-/* HSIO SS */
-#define IMX_HSIO_AXI_CLK				60
-#define IMX_HSIO_PER_CLK				61
-
-/* Display controller SS */
-#define IMX_DC_AXI_EXT_CLK				70
-#define IMX_DC_AXI_INT_CLK				71
-#define IMX_DC_CFG_CLK					72
-#define IMX_DC0_PLL0_CLK				80
-#define IMX_DC0_PLL1_CLK				81
-#define IMX_DC0_DISP0_CLK				82
-#define IMX_DC0_DISP1_CLK				83
-#define IMX_DC0_BYPASS0_CLK				84
-#define IMX_DC0_BYPASS1_CLK				85
-
-/* MIPI-LVDS SS */
-#define IMX_MIPI_IPG_CLK				90
-#define IMX_MIPI0_PIXEL_CLK				100
-#define IMX_MIPI0_BYPASS_CLK				101
-#define IMX_MIPI0_LVDS_PIXEL_CLK			102
-#define IMX_MIPI0_LVDS_BYPASS_CLK			103
-#define IMX_MIPI0_LVDS_PHY_CLK				104
-#define IMX_MIPI0_I2C0_CLK				105
-#define IMX_MIPI0_I2C1_CLK				106
-#define IMX_MIPI0_PWM0_CLK				107
-#define IMX_MIPI1_PIXEL_CLK				108
-#define IMX_MIPI1_BYPASS_CLK				109
-#define IMX_MIPI1_LVDS_PIXEL_CLK			110
-#define IMX_MIPI1_LVDS_BYPASS_CLK			111
-#define IMX_MIPI1_LVDS_PHY_CLK				112
-#define IMX_MIPI1_I2C0_CLK				113
-#define IMX_MIPI1_I2C1_CLK				114
-#define IMX_MIPI1_PWM0_CLK				115
-
-/* IMG SS */
-#define IMX_IMG_AXI_CLK					120
-#define IMX_IMG_IPG_CLK					121
-#define IMX_IMG_PXL_CLK					122
-
-/* MIPI-CSI SS */
-#define IMX_CSI0_CORE_CLK				130
-#define IMX_CSI0_ESC_CLK				131
-#define IMX_CSI0_PWM0_CLK				132
-#define IMX_CSI0_I2C0_CLK				133
-
-/* PARALLER CSI SS */
-#define IMX_PARALLEL_CSI_DPLL_CLK			140
-#define IMX_PARALLEL_CSI_PIXEL_CLK			141
-#define IMX_PARALLEL_CSI_MCLK_CLK			142
-
-/* VPU SS */
-#define IMX_VPU_ENC_CLK					150
-#define IMX_VPU_DEC_CLK					151
-
-/* GPU SS */
-#define IMX_GPU0_CORE_CLK				160
-#define IMX_GPU0_SHADER_CLK				161
-
-/* ADMA SS */
-#define IMX_ADMA_IPG_CLK_ROOT				165
-#define IMX_ADMA_UART0_CLK				170
-#define IMX_ADMA_UART1_CLK				171
-#define IMX_ADMA_UART2_CLK				172
-#define IMX_ADMA_UART3_CLK				173
-#define IMX_ADMA_SPI0_CLK				174
-#define IMX_ADMA_SPI1_CLK				175
-#define IMX_ADMA_SPI2_CLK				176
-#define IMX_ADMA_SPI3_CLK				177
-#define IMX_ADMA_CAN0_CLK				178
-#define IMX_ADMA_CAN1_CLK				179
-#define IMX_ADMA_CAN2_CLK				180
-#define IMX_ADMA_I2C0_CLK				181
-#define IMX_ADMA_I2C1_CLK				182
-#define IMX_ADMA_I2C2_CLK				183
-#define IMX_ADMA_I2C3_CLK				184
-#define IMX_ADMA_FTM0_CLK				185
-#define IMX_ADMA_FTM1_CLK				186
-#define IMX_ADMA_ADC0_CLK				187
-#define IMX_ADMA_PWM_CLK				188
-#define IMX_ADMA_LCD_CLK				189
-
-#define IMX_SCU_CLK_END					190
-
 /* LPCG clocks */
 
 /* LSIO SS LPCG */
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support
  2021-04-23  3:33 ` [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support Dong Aisheng
@ 2021-05-13 20:04   ` Abel Vesa
  0 siblings, 0 replies; 20+ messages in thread
From: Abel Vesa @ 2021-05-13 20:04 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-clk, linux-arm-kernel, dongas86, kernel, shawnguo,
	linux-imx, abel.vesa, sboyd

On 21-04-23 11:33:31, Dong Aisheng wrote:
> Legacy scu clock binding are not maintained anymore, it has a very
> limited clocks supported during initial upstreaming and obviously
> unusable by products. So it's meaningless to keep it in
> kernel which worse the code readability.
> Remove it to keep code much cleaner.
> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

I'm OK with this one too.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8qxp.c          | 201 ++++++++++---------------
>  drivers/clk/imx/clk-scu.h              |  15 +-
>  include/dt-bindings/clock/imx8-clock.h | 128 ----------------
>  3 files changed, 81 insertions(+), 263 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index fbf1170c09ed..d17b418ac577 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -14,7 +14,6 @@
>  
>  #include "clk-scu.h"
>  
> -#include <dt-bindings/clock/imx8-clock.h>
>  #include <dt-bindings/firmware/imx/rsrc.h>
>  
>  static const char *dc0_sels[] = {
> @@ -28,149 +27,103 @@ static const char *dc0_sels[] = {
>  static int imx8qxp_clk_probe(struct platform_device *pdev)
>  {
>  	struct device_node *ccm_node = pdev->dev.of_node;
> -	struct clk_hw_onecell_data *clk_data;
> -	struct clk_hw **clks;
> -	u32 clk_cells;
> -	int ret, i;
> +	int ret;
>  
>  	ret = imx_clk_scu_init(ccm_node);
>  	if (ret)
>  		return ret;
>  
> -	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
> -				IMX_SCU_CLK_END), GFP_KERNEL);
> -	if (!clk_data)
> -		return -ENOMEM;
> -
> -	if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
> -		return -EINVAL;
> -
> -	clk_data->num = IMX_SCU_CLK_END;
> -	clks = clk_data->hws;
> -
> -	/* Fixed clocks */
> -	clks[IMX_CLK_DUMMY]		= clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
> -	clks[IMX_ADMA_IPG_CLK_ROOT] 	= clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
> -	clks[IMX_CONN_AXI_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
> -	clks[IMX_CONN_AHB_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
> -	clks[IMX_CONN_IPG_CLK_ROOT]	= clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
> -	clks[IMX_DC_AXI_EXT_CLK]	= clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
> -	clks[IMX_DC_AXI_INT_CLK]	= clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
> -	clks[IMX_DC_CFG_CLK]		= clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
> -	clks[IMX_MIPI_IPG_CLK]		= clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
> -	clks[IMX_IMG_AXI_CLK]		= clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
> -	clks[IMX_IMG_IPG_CLK]		= clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
> -	clks[IMX_IMG_PXL_CLK]		= clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
> -	clks[IMX_HSIO_AXI_CLK]		= clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
> -	clks[IMX_HSIO_PER_CLK]		= clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
> -	clks[IMX_LSIO_MEM_CLK]		= clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
> -	clks[IMX_LSIO_BUS_CLK]		= clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
> -
>  	/* ARM core */
> -	clks[IMX_A35_CLK]		= imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
> +	imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
>  
>  	/* LSIO SS */
> -	clks[IMX_LSIO_PWM0_CLK]		= imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM1_CLK]		= imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM2_CLK]		= imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM3_CLK]		= imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM4_CLK]		= imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM5_CLK]		= imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM6_CLK]		= imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_PWM7_CLK]		= imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_GPT0_CLK]		= imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_GPT1_CLK]		= imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_GPT2_CLK]		= imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_GPT3_CLK]		= imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_GPT4_CLK]		= imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_FSPI0_CLK]	= imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_LSIO_FSPI1_CLK]	= imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
> +	imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
>  
>  	/* ADMA SS */
> -	clks[IMX_ADMA_UART0_CLK]	= imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_UART1_CLK]	= imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_UART2_CLK]	= imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_UART3_CLK]	= imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_SPI0_CLK]		= imx_clk_scu("spi0_clk",  IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_SPI1_CLK]		= imx_clk_scu("spi1_clk",  IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_SPI2_CLK]		= imx_clk_scu("spi2_clk",  IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_SPI3_CLK]		= imx_clk_scu("spi3_clk",  IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_CAN0_CLK]		= imx_clk_scu("can0_clk",  IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_I2C0_CLK]		= imx_clk_scu("i2c0_clk",  IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_I2C1_CLK]		= imx_clk_scu("i2c1_clk",  IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_I2C2_CLK]		= imx_clk_scu("i2c2_clk",  IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_I2C3_CLK]		= imx_clk_scu("i2c3_clk",  IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_FTM0_CLK]		= imx_clk_scu("ftm0_clk",  IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_FTM1_CLK]		= imx_clk_scu("ftm1_clk",  IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_ADC0_CLK]		= imx_clk_scu("adc0_clk",  IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_PWM_CLK]		= imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_ADMA_LCD_CLK]		= imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
> +	imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("spi0_clk",  IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("spi1_clk",  IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("spi2_clk",  IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("spi3_clk",  IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("can0_clk",  IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("i2c0_clk",  IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("i2c1_clk",  IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("i2c2_clk",  IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("i2c3_clk",  IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("ftm0_clk",  IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("ftm1_clk",  IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("adc0_clk",  IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
>  
>  	/* Connectivity */
> -	clks[IMX_CONN_SDHC0_CLK]	= imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_SDHC1_CLK]	= imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_SDHC2_CLK]	= imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_ENET0_ROOT_CLK]	= imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_ENET0_BYPASS_CLK]	= imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
> -	clks[IMX_CONN_ENET0_RGMII_CLK]	= imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
> -	clks[IMX_CONN_ENET1_ROOT_CLK]	= imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_ENET1_BYPASS_CLK]	= imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
> -	clks[IMX_CONN_ENET1_RGMII_CLK]	= imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
> -	clks[IMX_CONN_GPMI_BCH_IO_CLK]	= imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
> -	clks[IMX_CONN_GPMI_BCH_CLK]	= imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_USB2_ACLK]	= imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CONN_USB2_BUS_CLK]	= imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
> -	clks[IMX_CONN_USB2_LPM_CLK]	= imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
> +	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
> +	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
> +	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
> +	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
> +	imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
>  
>  	/* Display controller SS */
> -	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
> -	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
> -	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
> -	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
> -	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
> -	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
> +	imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
> +	imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
> +	imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
> +	imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
> +	imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
>  
>  	/* MIPI-LVDS SS */
> -	clks[IMX_MIPI0_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI0_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
> -	clks[IMX_MIPI0_LVDS_PHY_CLK]	= imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
> -	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI0_I2C1_CLK]	= imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI0_PWM0_CLK]	= imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_MIPI1_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI1_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
> -	clks[IMX_MIPI1_LVDS_PHY_CLK]	= imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
> -	clks[IMX_MIPI1_I2C0_CLK]	= imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI1_I2C1_CLK]	= imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
> -	clks[IMX_MIPI1_PWM0_CLK]	= imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
> +	imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
> +	imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
> +	imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
> +	imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
> +	imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
> +	imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
>  
>  	/* MIPI CSI SS */
> -	clks[IMX_CSI0_CORE_CLK]		= imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CSI0_ESC_CLK]		= imx_clk_scu("mipi_csi0_esc_clk",  IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
> -	clks[IMX_CSI0_I2C0_CLK]		= imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_CSI0_PWM0_CLK]		= imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
> +	imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("mipi_csi0_esc_clk",  IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
> +	imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
>  
>  	/* GPU SS */
> -	clks[IMX_GPU0_CORE_CLK]		= imx_clk_scu("gpu_core0_clk",	 IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
> -	clks[IMX_GPU0_SHADER_CLK]	= imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
> -
> -	for (i = 0; i < clk_data->num; i++) {
> -		if (IS_ERR(clks[i]))
> -			pr_warn("i.MX clk %u: register failed with %ld\n",
> -				i, PTR_ERR(clks[i]));
> -	}
> -
> -	if (clk_cells == 2) {
> -		ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
> -		if (ret)
> -			imx_clk_scu_unregister();
> -	} else {
> -		/*
> -		 * legacy binding code path doesn't unregister here because
> -		 * it will be removed later.
> -		 */
> -		ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
> -	}
> +	imx_clk_scu("gpu_core0_clk",	 IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
> +
> +	ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
> +	if (ret)
> +		imx_clk_scu_unregister();
>  
>  	return ret;
>  }
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> index e8352164923e..a6c6d3103e94 100644
> --- a/drivers/clk/imx/clk-scu.h
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -32,22 +32,15 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
>  void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
>  
>  static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
> -					 u8 clk_type, u8 clk_cells)
> +					 u8 clk_type)
>  {
> -	if (clk_cells == 2)
> -		return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
> -	else
> -		return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type);
> +	return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
>  }
>  
>  static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
> -					  int num_parents, u32 rsrc_id, u8 clk_type,
> -					  u8 clk_cells)
> +					  int num_parents, u32 rsrc_id, u8 clk_type)
>  {
> -	if (clk_cells == 2)
> -		return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
> -	else
> -		return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type);
> +	return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
>  }
>  
>  static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
> diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
> index 82b1fc8d1ee0..2e60ce4d2622 100644
> --- a/include/dt-bindings/clock/imx8-clock.h
> +++ b/include/dt-bindings/clock/imx8-clock.h
> @@ -7,134 +7,6 @@
>  #ifndef __DT_BINDINGS_CLOCK_IMX_H
>  #define __DT_BINDINGS_CLOCK_IMX_H
>  
> -/* SCU Clocks */
> -
> -#define IMX_CLK_DUMMY				0
> -
> -/* CPU */
> -#define IMX_A35_CLK					1
> -
> -/* LSIO SS */
> -#define IMX_LSIO_MEM_CLK				2
> -#define IMX_LSIO_BUS_CLK				3
> -#define IMX_LSIO_PWM0_CLK				10
> -#define IMX_LSIO_PWM1_CLK				11
> -#define IMX_LSIO_PWM2_CLK				12
> -#define IMX_LSIO_PWM3_CLK				13
> -#define IMX_LSIO_PWM4_CLK				14
> -#define IMX_LSIO_PWM5_CLK				15
> -#define IMX_LSIO_PWM6_CLK				16
> -#define IMX_LSIO_PWM7_CLK				17
> -#define IMX_LSIO_GPT0_CLK				18
> -#define IMX_LSIO_GPT1_CLK				19
> -#define IMX_LSIO_GPT2_CLK				20
> -#define IMX_LSIO_GPT3_CLK				21
> -#define IMX_LSIO_GPT4_CLK				22
> -#define IMX_LSIO_FSPI0_CLK				23
> -#define IMX_LSIO_FSPI1_CLK				24
> -
> -/* Connectivity SS */
> -#define IMX_CONN_AXI_CLK_ROOT				30
> -#define IMX_CONN_AHB_CLK_ROOT				31
> -#define IMX_CONN_IPG_CLK_ROOT				32
> -#define IMX_CONN_SDHC0_CLK				40
> -#define IMX_CONN_SDHC1_CLK				41
> -#define IMX_CONN_SDHC2_CLK				42
> -#define IMX_CONN_ENET0_ROOT_CLK				43
> -#define IMX_CONN_ENET0_BYPASS_CLK			44
> -#define IMX_CONN_ENET0_RGMII_CLK			45
> -#define IMX_CONN_ENET1_ROOT_CLK				46
> -#define IMX_CONN_ENET1_BYPASS_CLK			47
> -#define IMX_CONN_ENET1_RGMII_CLK			48
> -#define IMX_CONN_GPMI_BCH_IO_CLK			49
> -#define IMX_CONN_GPMI_BCH_CLK				50
> -#define IMX_CONN_USB2_ACLK				51
> -#define IMX_CONN_USB2_BUS_CLK				52
> -#define IMX_CONN_USB2_LPM_CLK				53
> -
> -/* HSIO SS */
> -#define IMX_HSIO_AXI_CLK				60
> -#define IMX_HSIO_PER_CLK				61
> -
> -/* Display controller SS */
> -#define IMX_DC_AXI_EXT_CLK				70
> -#define IMX_DC_AXI_INT_CLK				71
> -#define IMX_DC_CFG_CLK					72
> -#define IMX_DC0_PLL0_CLK				80
> -#define IMX_DC0_PLL1_CLK				81
> -#define IMX_DC0_DISP0_CLK				82
> -#define IMX_DC0_DISP1_CLK				83
> -#define IMX_DC0_BYPASS0_CLK				84
> -#define IMX_DC0_BYPASS1_CLK				85
> -
> -/* MIPI-LVDS SS */
> -#define IMX_MIPI_IPG_CLK				90
> -#define IMX_MIPI0_PIXEL_CLK				100
> -#define IMX_MIPI0_BYPASS_CLK				101
> -#define IMX_MIPI0_LVDS_PIXEL_CLK			102
> -#define IMX_MIPI0_LVDS_BYPASS_CLK			103
> -#define IMX_MIPI0_LVDS_PHY_CLK				104
> -#define IMX_MIPI0_I2C0_CLK				105
> -#define IMX_MIPI0_I2C1_CLK				106
> -#define IMX_MIPI0_PWM0_CLK				107
> -#define IMX_MIPI1_PIXEL_CLK				108
> -#define IMX_MIPI1_BYPASS_CLK				109
> -#define IMX_MIPI1_LVDS_PIXEL_CLK			110
> -#define IMX_MIPI1_LVDS_BYPASS_CLK			111
> -#define IMX_MIPI1_LVDS_PHY_CLK				112
> -#define IMX_MIPI1_I2C0_CLK				113
> -#define IMX_MIPI1_I2C1_CLK				114
> -#define IMX_MIPI1_PWM0_CLK				115
> -
> -/* IMG SS */
> -#define IMX_IMG_AXI_CLK					120
> -#define IMX_IMG_IPG_CLK					121
> -#define IMX_IMG_PXL_CLK					122
> -
> -/* MIPI-CSI SS */
> -#define IMX_CSI0_CORE_CLK				130
> -#define IMX_CSI0_ESC_CLK				131
> -#define IMX_CSI0_PWM0_CLK				132
> -#define IMX_CSI0_I2C0_CLK				133
> -
> -/* PARALLER CSI SS */
> -#define IMX_PARALLEL_CSI_DPLL_CLK			140
> -#define IMX_PARALLEL_CSI_PIXEL_CLK			141
> -#define IMX_PARALLEL_CSI_MCLK_CLK			142
> -
> -/* VPU SS */
> -#define IMX_VPU_ENC_CLK					150
> -#define IMX_VPU_DEC_CLK					151
> -
> -/* GPU SS */
> -#define IMX_GPU0_CORE_CLK				160
> -#define IMX_GPU0_SHADER_CLK				161
> -
> -/* ADMA SS */
> -#define IMX_ADMA_IPG_CLK_ROOT				165
> -#define IMX_ADMA_UART0_CLK				170
> -#define IMX_ADMA_UART1_CLK				171
> -#define IMX_ADMA_UART2_CLK				172
> -#define IMX_ADMA_UART3_CLK				173
> -#define IMX_ADMA_SPI0_CLK				174
> -#define IMX_ADMA_SPI1_CLK				175
> -#define IMX_ADMA_SPI2_CLK				176
> -#define IMX_ADMA_SPI3_CLK				177
> -#define IMX_ADMA_CAN0_CLK				178
> -#define IMX_ADMA_CAN1_CLK				179
> -#define IMX_ADMA_CAN2_CLK				180
> -#define IMX_ADMA_I2C0_CLK				181
> -#define IMX_ADMA_I2C1_CLK				182
> -#define IMX_ADMA_I2C2_CLK				183
> -#define IMX_ADMA_I2C3_CLK				184
> -#define IMX_ADMA_FTM0_CLK				185
> -#define IMX_ADMA_FTM1_CLK				186
> -#define IMX_ADMA_ADC0_CLK				187
> -#define IMX_ADMA_PWM_CLK				188
> -#define IMX_ADMA_LCD_CLK				189
> -
> -#define IMX_SCU_CLK_END					190
> -
>  /* LPCG clocks */
>  
>  /* LSIO SS LPCG */
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 4/6] clk: imx: scu: add gpr clocks support
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
  2021-04-23  3:33 ` [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding Dong Aisheng
  2021-04-23  3:33 ` [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support Dong Aisheng
@ 2021-04-23  3:33 ` Dong Aisheng
  2021-05-13  6:58   ` Abel Vesa
  2021-04-23  3:33 ` [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism Dong Aisheng
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd, Dong Aisheng

SCU clock protocol supports a few clocks based on GPR controller
registers including mux/divider/gate.
And a general clock register API to support them all.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/clk-scu.c | 186 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-scu.h |  29 ++++++
 2 files changed, 215 insertions(+)

diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index 1f5518b7ab39..cff0e1bd7030 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -52,6 +52,22 @@ struct clk_scu {
 	u32 rate;
 };
 
+/*
+ * struct clk_gpr_scu - Description of one SCU GPR clock
+ * @hw: the common clk_hw
+ * @rsrc_id: resource ID of this SCU clock
+ * @gpr_id: GPR ID index to control the divider
+ */
+struct clk_gpr_scu {
+	struct clk_hw hw;
+	u16 rsrc_id;
+	u8 gpr_id;
+	u8 flags;
+	bool gate_invert;
+};
+
+#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
+
 /*
  * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
  * @hdr: SCU protocol header
@@ -604,3 +620,173 @@ void imx_clk_scu_unregister(void)
 		}
 	}
 }
+
+static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
+						 unsigned long parent_rate)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+	unsigned long rate = 0;
+	u32 val;
+	int err;
+
+	err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
+				      clk->gpr_id, &val);
+
+	rate  = val ? parent_rate / 2 : parent_rate;
+
+	return err ? 0 : rate;
+}
+
+static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
+				   unsigned long *prate)
+{
+	if (rate < *prate)
+		rate = *prate / 2;
+	else
+		rate = *prate;
+
+	return rate;
+}
+
+static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long parent_rate)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+	uint32_t val;
+	int err;
+
+	val = (rate < parent_rate) ? 1 : 0;
+	err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
+				      clk->gpr_id, val);
+
+	return err ? -EINVAL : 0;
+}
+
+static const struct clk_ops clk_gpr_div_scu_ops = {
+	.recalc_rate = clk_gpr_div_scu_recalc_rate,
+	.round_rate = clk_gpr_div_scu_round_rate,
+	.set_rate = clk_gpr_div_scu_set_rate,
+};
+
+static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+	u32 val = 0;
+
+	imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
+				clk->gpr_id, &val);
+
+	return (u8)val;
+}
+
+static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+
+	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
+				       clk->gpr_id, index);
+}
+
+static const struct clk_ops clk_gpr_mux_scu_ops = {
+	.get_parent = clk_gpr_mux_scu_get_parent,
+	.set_parent = clk_gpr_mux_scu_set_parent,
+};
+
+static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+
+	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
+				       clk->gpr_id, !clk->gate_invert);
+}
+
+static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+	int ret;
+
+	ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
+				      clk->gpr_id, clk->gate_invert);
+	if (ret)
+		pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
+		       ret);
+}
+
+static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
+{
+	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
+	int ret;
+	u32 val;
+
+	ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
+				      clk->gpr_id, &val);
+	if (ret)
+		return ret;
+
+	return clk->gate_invert ? !val : val;
+}
+
+static const struct clk_ops clk_gpr_gate_scu_ops = {
+	.prepare = clk_gpr_gate_scu_prepare,
+	.unprepare = clk_gpr_gate_scu_unprepare,
+	.is_prepared = clk_gpr_gate_scu_is_prepared,
+};
+
+struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
+				 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
+				 bool invert)
+{
+	struct imx_scu_clk_node *clk_node;
+	struct clk_gpr_scu *clk;
+	struct clk_hw *hw;
+	struct clk_init_data init;
+	int ret;
+
+	if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
+		return ERR_PTR(-EINVAL);
+
+	clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
+	if (!clk_node)
+		return ERR_PTR(-ENOMEM);
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk) {
+		kfree(clk_node);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk->rsrc_id = rsrc_id;
+	clk->gpr_id = gpr_id;
+	clk->flags = flags;
+	clk->gate_invert = invert;
+
+	if (flags & IMX_SCU_GPR_CLK_GATE)
+		init.ops = &clk_gpr_gate_scu_ops;
+
+	if (flags & IMX_SCU_GPR_CLK_DIV)
+		init.ops = &clk_gpr_div_scu_ops;
+
+	if (flags & IMX_SCU_GPR_CLK_MUX)
+		init.ops = &clk_gpr_mux_scu_ops;
+
+	init.flags = 0;
+	init.name = name;
+	init.parent_names = parent_name;
+	init.num_parents = num_parents;
+
+	clk->hw.init = &init;
+
+	hw = &clk->hw;
+	ret = clk_hw_register(NULL, hw);
+	if (ret) {
+		kfree(clk);
+		kfree(clk_node);
+		hw = ERR_PTR(ret);
+	} else {
+		clk_node->hw = hw;
+		clk_node->clk_type = gpr_id;
+		list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
+	}
+
+	return hw;
+}
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index a6c6d3103e94..8ebee0cb0fe6 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -10,6 +10,10 @@
 #include <linux/firmware/imx/sci.h>
 #include <linux/of.h>
 
+#define IMX_SCU_GPR_CLK_GATE	BIT(0)
+#define IMX_SCU_GPR_CLK_DIV	BIT(1)
+#define IMX_SCU_GPR_CLK_MUX	BIT(2)
+
 extern struct list_head imx_scu_clks[];
 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
 
@@ -31,6 +35,10 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
 				  void __iomem *reg, u8 bit_idx, bool hw_gate);
 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
 
+struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
+				 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
+				 bool invert);
+
 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
 					 u8 clk_type)
 {
@@ -58,4 +66,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
 	return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
 				  bit_idx, hw_gate);
 }
+
+static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
+						  u32 rsrc_id, u8 gpr_id, bool invert)
+{
+	return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
+				 IMX_SCU_GPR_CLK_GATE, invert);
+}
+
+static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
+						     u32 rsrc_id, u8 gpr_id)
+{
+	return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
+				 IMX_SCU_GPR_CLK_DIV, 0);
+}
+
+static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
+						 int num_parents, u32 rsrc_id, u8 gpr_id)
+{
+	return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
+				 gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
+}
 #endif
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/6] clk: imx: scu: add gpr clocks support
  2021-04-23  3:33 ` [PATCH 4/6] clk: imx: scu: add gpr clocks support Dong Aisheng
@ 2021-05-13  6:58   ` Abel Vesa
  2021-05-17  9:49     ` Dong Aisheng
  0 siblings, 1 reply; 20+ messages in thread
From: Abel Vesa @ 2021-05-13  6:58 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-clk, linux-arm-kernel, dongas86, kernel, shawnguo,
	linux-imx, abel.vesa, sboyd

On 21-04-23 11:33:32, Dong Aisheng wrote:
> SCU clock protocol supports a few clocks based on GPR controller
> registers including mux/divider/gate.
> And a general clock register API to support them all.

You mean "Add a generic", right ?

Otherwise, looks OK to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  drivers/clk/imx/clk-scu.c | 186 ++++++++++++++++++++++++++++++++++++++
>  drivers/clk/imx/clk-scu.h |  29 ++++++
>  2 files changed, 215 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> index 1f5518b7ab39..cff0e1bd7030 100644
> --- a/drivers/clk/imx/clk-scu.c
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -52,6 +52,22 @@ struct clk_scu {
>  	u32 rate;
>  };
>  
> +/*
> + * struct clk_gpr_scu - Description of one SCU GPR clock
> + * @hw: the common clk_hw
> + * @rsrc_id: resource ID of this SCU clock
> + * @gpr_id: GPR ID index to control the divider
> + */
> +struct clk_gpr_scu {
> +	struct clk_hw hw;
> +	u16 rsrc_id;
> +	u8 gpr_id;
> +	u8 flags;
> +	bool gate_invert;
> +};
> +
> +#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
> +
>  /*
>   * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
>   * @hdr: SCU protocol header
> @@ -604,3 +620,173 @@ void imx_clk_scu_unregister(void)
>  		}
>  	}
>  }
> +
> +static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
> +						 unsigned long parent_rate)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +	unsigned long rate = 0;
> +	u32 val;
> +	int err;
> +
> +	err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> +				      clk->gpr_id, &val);
> +
> +	rate  = val ? parent_rate / 2 : parent_rate;
> +
> +	return err ? 0 : rate;
> +}
> +
> +static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
> +				   unsigned long *prate)
> +{
> +	if (rate < *prate)
> +		rate = *prate / 2;
> +	else
> +		rate = *prate;
> +
> +	return rate;
> +}
> +
> +static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
> +				    unsigned long parent_rate)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +	uint32_t val;
> +	int err;
> +
> +	val = (rate < parent_rate) ? 1 : 0;
> +	err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> +				      clk->gpr_id, val);
> +
> +	return err ? -EINVAL : 0;
> +}
> +
> +static const struct clk_ops clk_gpr_div_scu_ops = {
> +	.recalc_rate = clk_gpr_div_scu_recalc_rate,
> +	.round_rate = clk_gpr_div_scu_round_rate,
> +	.set_rate = clk_gpr_div_scu_set_rate,
> +};
> +
> +static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +	u32 val = 0;
> +
> +	imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> +				clk->gpr_id, &val);
> +
> +	return (u8)val;
> +}
> +
> +static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +
> +	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> +				       clk->gpr_id, index);
> +}
> +
> +static const struct clk_ops clk_gpr_mux_scu_ops = {
> +	.get_parent = clk_gpr_mux_scu_get_parent,
> +	.set_parent = clk_gpr_mux_scu_set_parent,
> +};
> +
> +static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +
> +	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> +				       clk->gpr_id, !clk->gate_invert);
> +}
> +
> +static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +	int ret;
> +
> +	ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> +				      clk->gpr_id, clk->gate_invert);
> +	if (ret)
> +		pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
> +		       ret);
> +}
> +
> +static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
> +{
> +	struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> +	int ret;
> +	u32 val;
> +
> +	ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> +				      clk->gpr_id, &val);
> +	if (ret)
> +		return ret;
> +
> +	return clk->gate_invert ? !val : val;
> +}
> +
> +static const struct clk_ops clk_gpr_gate_scu_ops = {
> +	.prepare = clk_gpr_gate_scu_prepare,
> +	.unprepare = clk_gpr_gate_scu_unprepare,
> +	.is_prepared = clk_gpr_gate_scu_is_prepared,
> +};
> +
> +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> +				 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> +				 bool invert)
> +{
> +	struct imx_scu_clk_node *clk_node;
> +	struct clk_gpr_scu *clk;
> +	struct clk_hw *hw;
> +	struct clk_init_data init;
> +	int ret;
> +
> +	if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
> +		return ERR_PTR(-EINVAL);
> +
> +	clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
> +	if (!clk_node)
> +		return ERR_PTR(-ENOMEM);
> +
> +	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> +	if (!clk) {
> +		kfree(clk_node);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	clk->rsrc_id = rsrc_id;
> +	clk->gpr_id = gpr_id;
> +	clk->flags = flags;
> +	clk->gate_invert = invert;
> +
> +	if (flags & IMX_SCU_GPR_CLK_GATE)
> +		init.ops = &clk_gpr_gate_scu_ops;
> +
> +	if (flags & IMX_SCU_GPR_CLK_DIV)
> +		init.ops = &clk_gpr_div_scu_ops;
> +
> +	if (flags & IMX_SCU_GPR_CLK_MUX)
> +		init.ops = &clk_gpr_mux_scu_ops;
> +
> +	init.flags = 0;
> +	init.name = name;
> +	init.parent_names = parent_name;
> +	init.num_parents = num_parents;
> +
> +	clk->hw.init = &init;
> +
> +	hw = &clk->hw;
> +	ret = clk_hw_register(NULL, hw);
> +	if (ret) {
> +		kfree(clk);
> +		kfree(clk_node);
> +		hw = ERR_PTR(ret);
> +	} else {
> +		clk_node->hw = hw;
> +		clk_node->clk_type = gpr_id;
> +		list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
> +	}
> +
> +	return hw;
> +}
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> index a6c6d3103e94..8ebee0cb0fe6 100644
> --- a/drivers/clk/imx/clk-scu.h
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -10,6 +10,10 @@
>  #include <linux/firmware/imx/sci.h>
>  #include <linux/of.h>
>  
> +#define IMX_SCU_GPR_CLK_GATE	BIT(0)
> +#define IMX_SCU_GPR_CLK_DIV	BIT(1)
> +#define IMX_SCU_GPR_CLK_MUX	BIT(2)
> +
>  extern struct list_head imx_scu_clks[];
>  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
>  
> @@ -31,6 +35,10 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
>  				  void __iomem *reg, u8 bit_idx, bool hw_gate);
>  void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
>  
> +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> +				 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> +				 bool invert);
> +
>  static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
>  					 u8 clk_type)
>  {
> @@ -58,4 +66,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
>  	return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
>  				  bit_idx, hw_gate);
>  }
> +
> +static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
> +						  u32 rsrc_id, u8 gpr_id, bool invert)
> +{
> +	return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> +				 IMX_SCU_GPR_CLK_GATE, invert);
> +}
> +
> +static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
> +						     u32 rsrc_id, u8 gpr_id)
> +{
> +	return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> +				 IMX_SCU_GPR_CLK_DIV, 0);
> +}
> +
> +static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
> +						 int num_parents, u32 rsrc_id, u8 gpr_id)
> +{
> +	return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
> +				 gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
> +}
>  #endif
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/6] clk: imx: scu: add gpr clocks support
  2021-05-13  6:58   ` Abel Vesa
@ 2021-05-17  9:49     ` Dong Aisheng
  2021-05-17  9:52       ` Abel Vesa
  0 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-05-17  9:49 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Dong Aisheng, linux-clk,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Sascha Hauer, Shawn Guo, dl-linux-imx, Abel Vesa, Stephen Boyd

On Thu, May 13, 2021 at 2:58 PM Abel Vesa <abelvesa@kernel.org> wrote:
>
> On 21-04-23 11:33:32, Dong Aisheng wrote:
> > SCU clock protocol supports a few clocks based on GPR controller
> > registers including mux/divider/gate.
> > And a general clock register API to support them all.
>
> You mean "Add a generic", right ?

Good catch.
Please let me know if you want a resend.
Thanks

Regards
Aisheng

>
> Otherwise, looks OK to me.
>
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
>
> >
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> >  drivers/clk/imx/clk-scu.c | 186 ++++++++++++++++++++++++++++++++++++++
> >  drivers/clk/imx/clk-scu.h |  29 ++++++
> >  2 files changed, 215 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> > index 1f5518b7ab39..cff0e1bd7030 100644
> > --- a/drivers/clk/imx/clk-scu.c
> > +++ b/drivers/clk/imx/clk-scu.c
> > @@ -52,6 +52,22 @@ struct clk_scu {
> >       u32 rate;
> >  };
> >
> > +/*
> > + * struct clk_gpr_scu - Description of one SCU GPR clock
> > + * @hw: the common clk_hw
> > + * @rsrc_id: resource ID of this SCU clock
> > + * @gpr_id: GPR ID index to control the divider
> > + */
> > +struct clk_gpr_scu {
> > +     struct clk_hw hw;
> > +     u16 rsrc_id;
> > +     u8 gpr_id;
> > +     u8 flags;
> > +     bool gate_invert;
> > +};
> > +
> > +#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
> > +
> >  /*
> >   * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
> >   * @hdr: SCU protocol header
> > @@ -604,3 +620,173 @@ void imx_clk_scu_unregister(void)
> >               }
> >       }
> >  }
> > +
> > +static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
> > +                                              unsigned long parent_rate)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +     unsigned long rate = 0;
> > +     u32 val;
> > +     int err;
> > +
> > +     err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                   clk->gpr_id, &val);
> > +
> > +     rate  = val ? parent_rate / 2 : parent_rate;
> > +
> > +     return err ? 0 : rate;
> > +}
> > +
> > +static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
> > +                                unsigned long *prate)
> > +{
> > +     if (rate < *prate)
> > +             rate = *prate / 2;
> > +     else
> > +             rate = *prate;
> > +
> > +     return rate;
> > +}
> > +
> > +static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
> > +                                 unsigned long parent_rate)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +     uint32_t val;
> > +     int err;
> > +
> > +     val = (rate < parent_rate) ? 1 : 0;
> > +     err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                   clk->gpr_id, val);
> > +
> > +     return err ? -EINVAL : 0;
> > +}
> > +
> > +static const struct clk_ops clk_gpr_div_scu_ops = {
> > +     .recalc_rate = clk_gpr_div_scu_recalc_rate,
> > +     .round_rate = clk_gpr_div_scu_round_rate,
> > +     .set_rate = clk_gpr_div_scu_set_rate,
> > +};
> > +
> > +static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +     u32 val = 0;
> > +
> > +     imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > +                             clk->gpr_id, &val);
> > +
> > +     return (u8)val;
> > +}
> > +
> > +static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +
> > +     return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                    clk->gpr_id, index);
> > +}
> > +
> > +static const struct clk_ops clk_gpr_mux_scu_ops = {
> > +     .get_parent = clk_gpr_mux_scu_get_parent,
> > +     .set_parent = clk_gpr_mux_scu_set_parent,
> > +};
> > +
> > +static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +
> > +     return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                    clk->gpr_id, !clk->gate_invert);
> > +}
> > +
> > +static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +     int ret;
> > +
> > +     ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                   clk->gpr_id, clk->gate_invert);
> > +     if (ret)
> > +             pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
> > +                    ret);
> > +}
> > +
> > +static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
> > +{
> > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > +     int ret;
> > +     u32 val;
> > +
> > +     ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > +                                   clk->gpr_id, &val);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return clk->gate_invert ? !val : val;
> > +}
> > +
> > +static const struct clk_ops clk_gpr_gate_scu_ops = {
> > +     .prepare = clk_gpr_gate_scu_prepare,
> > +     .unprepare = clk_gpr_gate_scu_unprepare,
> > +     .is_prepared = clk_gpr_gate_scu_is_prepared,
> > +};
> > +
> > +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> > +                              int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> > +                              bool invert)
> > +{
> > +     struct imx_scu_clk_node *clk_node;
> > +     struct clk_gpr_scu *clk;
> > +     struct clk_hw *hw;
> > +     struct clk_init_data init;
> > +     int ret;
> > +
> > +     if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
> > +             return ERR_PTR(-EINVAL);
> > +
> > +     clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
> > +     if (!clk_node)
> > +             return ERR_PTR(-ENOMEM);
> > +
> > +     clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> > +     if (!clk) {
> > +             kfree(clk_node);
> > +             return ERR_PTR(-ENOMEM);
> > +     }
> > +
> > +     clk->rsrc_id = rsrc_id;
> > +     clk->gpr_id = gpr_id;
> > +     clk->flags = flags;
> > +     clk->gate_invert = invert;
> > +
> > +     if (flags & IMX_SCU_GPR_CLK_GATE)
> > +             init.ops = &clk_gpr_gate_scu_ops;
> > +
> > +     if (flags & IMX_SCU_GPR_CLK_DIV)
> > +             init.ops = &clk_gpr_div_scu_ops;
> > +
> > +     if (flags & IMX_SCU_GPR_CLK_MUX)
> > +             init.ops = &clk_gpr_mux_scu_ops;
> > +
> > +     init.flags = 0;
> > +     init.name = name;
> > +     init.parent_names = parent_name;
> > +     init.num_parents = num_parents;
> > +
> > +     clk->hw.init = &init;
> > +
> > +     hw = &clk->hw;
> > +     ret = clk_hw_register(NULL, hw);
> > +     if (ret) {
> > +             kfree(clk);
> > +             kfree(clk_node);
> > +             hw = ERR_PTR(ret);
> > +     } else {
> > +             clk_node->hw = hw;
> > +             clk_node->clk_type = gpr_id;
> > +             list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
> > +     }
> > +
> > +     return hw;
> > +}
> > diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> > index a6c6d3103e94..8ebee0cb0fe6 100644
> > --- a/drivers/clk/imx/clk-scu.h
> > +++ b/drivers/clk/imx/clk-scu.h
> > @@ -10,6 +10,10 @@
> >  #include <linux/firmware/imx/sci.h>
> >  #include <linux/of.h>
> >
> > +#define IMX_SCU_GPR_CLK_GATE BIT(0)
> > +#define IMX_SCU_GPR_CLK_DIV  BIT(1)
> > +#define IMX_SCU_GPR_CLK_MUX  BIT(2)
> > +
> >  extern struct list_head imx_scu_clks[];
> >  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
> >
> > @@ -31,6 +35,10 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
> >                                 void __iomem *reg, u8 bit_idx, bool hw_gate);
> >  void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
> >
> > +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> > +                              int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> > +                              bool invert);
> > +
> >  static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
> >                                        u8 clk_type)
> >  {
> > @@ -58,4 +66,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
> >       return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
> >                                 bit_idx, hw_gate);
> >  }
> > +
> > +static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
> > +                                               u32 rsrc_id, u8 gpr_id, bool invert)
> > +{
> > +     return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> > +                              IMX_SCU_GPR_CLK_GATE, invert);
> > +}
> > +
> > +static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
> > +                                                  u32 rsrc_id, u8 gpr_id)
> > +{
> > +     return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> > +                              IMX_SCU_GPR_CLK_DIV, 0);
> > +}
> > +
> > +static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
> > +                                              int num_parents, u32 rsrc_id, u8 gpr_id)
> > +{
> > +     return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
> > +                              gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
> > +}
> >  #endif
> > --
> > 2.25.1
> >

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/6] clk: imx: scu: add gpr clocks support
  2021-05-17  9:49     ` Dong Aisheng
@ 2021-05-17  9:52       ` Abel Vesa
  0 siblings, 0 replies; 20+ messages in thread
From: Abel Vesa @ 2021-05-17  9:52 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Dong Aisheng, linux-clk,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Sascha Hauer, Shawn Guo, dl-linux-imx, Stephen Boyd

On 21-05-17 17:49:08, Dong Aisheng wrote:
> On Thu, May 13, 2021 at 2:58 PM Abel Vesa <abelvesa@kernel.org> wrote:
> >
> > On 21-04-23 11:33:32, Dong Aisheng wrote:
> > > SCU clock protocol supports a few clocks based on GPR controller
> > > registers including mux/divider/gate.
> > > And a general clock register API to support them all.
> >
> > You mean "Add a generic", right ?
> 
> Good catch.
> Please let me know if you want a resend.
> Thanks
> 

No need to resend. I'll reword it myself.

Thanks.

> Regards
> Aisheng
> 
> >
> > Otherwise, looks OK to me.
> >
> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> >
> > >
> > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > > ---
> > >  drivers/clk/imx/clk-scu.c | 186 ++++++++++++++++++++++++++++++++++++++
> > >  drivers/clk/imx/clk-scu.h |  29 ++++++
> > >  2 files changed, 215 insertions(+)
> > >
> > > diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> > > index 1f5518b7ab39..cff0e1bd7030 100644
> > > --- a/drivers/clk/imx/clk-scu.c
> > > +++ b/drivers/clk/imx/clk-scu.c
> > > @@ -52,6 +52,22 @@ struct clk_scu {
> > >       u32 rate;
> > >  };
> > >
> > > +/*
> > > + * struct clk_gpr_scu - Description of one SCU GPR clock
> > > + * @hw: the common clk_hw
> > > + * @rsrc_id: resource ID of this SCU clock
> > > + * @gpr_id: GPR ID index to control the divider
> > > + */
> > > +struct clk_gpr_scu {
> > > +     struct clk_hw hw;
> > > +     u16 rsrc_id;
> > > +     u8 gpr_id;
> > > +     u8 flags;
> > > +     bool gate_invert;
> > > +};
> > > +
> > > +#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
> > > +
> > >  /*
> > >   * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
> > >   * @hdr: SCU protocol header
> > > @@ -604,3 +620,173 @@ void imx_clk_scu_unregister(void)
> > >               }
> > >       }
> > >  }
> > > +
> > > +static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
> > > +                                              unsigned long parent_rate)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +     unsigned long rate = 0;
> > > +     u32 val;
> > > +     int err;
> > > +
> > > +     err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                   clk->gpr_id, &val);
> > > +
> > > +     rate  = val ? parent_rate / 2 : parent_rate;
> > > +
> > > +     return err ? 0 : rate;
> > > +}
> > > +
> > > +static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
> > > +                                unsigned long *prate)
> > > +{
> > > +     if (rate < *prate)
> > > +             rate = *prate / 2;
> > > +     else
> > > +             rate = *prate;
> > > +
> > > +     return rate;
> > > +}
> > > +
> > > +static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
> > > +                                 unsigned long parent_rate)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +     uint32_t val;
> > > +     int err;
> > > +
> > > +     val = (rate < parent_rate) ? 1 : 0;
> > > +     err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                   clk->gpr_id, val);
> > > +
> > > +     return err ? -EINVAL : 0;
> > > +}
> > > +
> > > +static const struct clk_ops clk_gpr_div_scu_ops = {
> > > +     .recalc_rate = clk_gpr_div_scu_recalc_rate,
> > > +     .round_rate = clk_gpr_div_scu_round_rate,
> > > +     .set_rate = clk_gpr_div_scu_set_rate,
> > > +};
> > > +
> > > +static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +     u32 val = 0;
> > > +
> > > +     imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                             clk->gpr_id, &val);
> > > +
> > > +     return (u8)val;
> > > +}
> > > +
> > > +static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +
> > > +     return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                    clk->gpr_id, index);
> > > +}
> > > +
> > > +static const struct clk_ops clk_gpr_mux_scu_ops = {
> > > +     .get_parent = clk_gpr_mux_scu_get_parent,
> > > +     .set_parent = clk_gpr_mux_scu_set_parent,
> > > +};
> > > +
> > > +static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +
> > > +     return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                    clk->gpr_id, !clk->gate_invert);
> > > +}
> > > +
> > > +static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +     int ret;
> > > +
> > > +     ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                   clk->gpr_id, clk->gate_invert);
> > > +     if (ret)
> > > +             pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
> > > +                    ret);
> > > +}
> > > +
> > > +static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
> > > +{
> > > +     struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
> > > +     int ret;
> > > +     u32 val;
> > > +
> > > +     ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
> > > +                                   clk->gpr_id, &val);
> > > +     if (ret)
> > > +             return ret;
> > > +
> > > +     return clk->gate_invert ? !val : val;
> > > +}
> > > +
> > > +static const struct clk_ops clk_gpr_gate_scu_ops = {
> > > +     .prepare = clk_gpr_gate_scu_prepare,
> > > +     .unprepare = clk_gpr_gate_scu_unprepare,
> > > +     .is_prepared = clk_gpr_gate_scu_is_prepared,
> > > +};
> > > +
> > > +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> > > +                              int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> > > +                              bool invert)
> > > +{
> > > +     struct imx_scu_clk_node *clk_node;
> > > +     struct clk_gpr_scu *clk;
> > > +     struct clk_hw *hw;
> > > +     struct clk_init_data init;
> > > +     int ret;
> > > +
> > > +     if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
> > > +             return ERR_PTR(-EINVAL);
> > > +
> > > +     clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
> > > +     if (!clk_node)
> > > +             return ERR_PTR(-ENOMEM);
> > > +
> > > +     clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> > > +     if (!clk) {
> > > +             kfree(clk_node);
> > > +             return ERR_PTR(-ENOMEM);
> > > +     }
> > > +
> > > +     clk->rsrc_id = rsrc_id;
> > > +     clk->gpr_id = gpr_id;
> > > +     clk->flags = flags;
> > > +     clk->gate_invert = invert;
> > > +
> > > +     if (flags & IMX_SCU_GPR_CLK_GATE)
> > > +             init.ops = &clk_gpr_gate_scu_ops;
> > > +
> > > +     if (flags & IMX_SCU_GPR_CLK_DIV)
> > > +             init.ops = &clk_gpr_div_scu_ops;
> > > +
> > > +     if (flags & IMX_SCU_GPR_CLK_MUX)
> > > +             init.ops = &clk_gpr_mux_scu_ops;
> > > +
> > > +     init.flags = 0;
> > > +     init.name = name;
> > > +     init.parent_names = parent_name;
> > > +     init.num_parents = num_parents;
> > > +
> > > +     clk->hw.init = &init;
> > > +
> > > +     hw = &clk->hw;
> > > +     ret = clk_hw_register(NULL, hw);
> > > +     if (ret) {
> > > +             kfree(clk);
> > > +             kfree(clk_node);
> > > +             hw = ERR_PTR(ret);
> > > +     } else {
> > > +             clk_node->hw = hw;
> > > +             clk_node->clk_type = gpr_id;
> > > +             list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
> > > +     }
> > > +
> > > +     return hw;
> > > +}
> > > diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> > > index a6c6d3103e94..8ebee0cb0fe6 100644
> > > --- a/drivers/clk/imx/clk-scu.h
> > > +++ b/drivers/clk/imx/clk-scu.h
> > > @@ -10,6 +10,10 @@
> > >  #include <linux/firmware/imx/sci.h>
> > >  #include <linux/of.h>
> > >
> > > +#define IMX_SCU_GPR_CLK_GATE BIT(0)
> > > +#define IMX_SCU_GPR_CLK_DIV  BIT(1)
> > > +#define IMX_SCU_GPR_CLK_MUX  BIT(2)
> > > +
> > >  extern struct list_head imx_scu_clks[];
> > >  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
> > >
> > > @@ -31,6 +35,10 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
> > >                                 void __iomem *reg, u8 bit_idx, bool hw_gate);
> > >  void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
> > >
> > > +struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
> > > +                              int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
> > > +                              bool invert);
> > > +
> > >  static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
> > >                                        u8 clk_type)
> > >  {
> > > @@ -58,4 +66,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
> > >       return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
> > >                                 bit_idx, hw_gate);
> > >  }
> > > +
> > > +static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
> > > +                                               u32 rsrc_id, u8 gpr_id, bool invert)
> > > +{
> > > +     return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> > > +                              IMX_SCU_GPR_CLK_GATE, invert);
> > > +}
> > > +
> > > +static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
> > > +                                                  u32 rsrc_id, u8 gpr_id)
> > > +{
> > > +     return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
> > > +                              IMX_SCU_GPR_CLK_DIV, 0);
> > > +}
> > > +
> > > +static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
> > > +                                              int num_parents, u32 rsrc_id, u8 gpr_id)
> > > +{
> > > +     return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
> > > +                              gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
> > > +}
> > >  #endif
> > > --
> > > 2.25.1
> > >

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
                   ` (2 preceding siblings ...)
  2021-04-23  3:33 ` [PATCH 4/6] clk: imx: scu: add gpr clocks support Dong Aisheng
@ 2021-04-23  3:33 ` Dong Aisheng
  2021-05-13  7:13   ` Abel Vesa
  2021-04-23  3:33 ` [PATCH 6/6] clk: imx8qm: add clock valid resource checking Dong Aisheng
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd, Dong Aisheng

clk-imx8qxp is a common SCU clock driver used by both QM and QXP
platforms. The clock numbers vary a bit between those two platforms.
This patch introduces a mechanism to only register the valid clocks
for one platform by checking the clk resource id table.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/Makefile           |  3 +-
 drivers/clk/imx/clk-imx8qxp-rsrc.c | 89 ++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp.c      |  9 ++-
 drivers/clk/imx/clk-scu.c          | 33 ++++++++++-
 drivers/clk/imx/clk-scu.h          | 11 +++-
 5 files changed, 137 insertions(+), 8 deletions(-)
 create mode 100644 drivers/clk/imx/clk-imx8qxp-rsrc.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index dd6a737d060b..2fdd2fff16c7 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
 obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
 
 obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
-clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
+clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
+				     clk-imx8qxp-rsrc.o
 clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
 
 obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
diff --git a/drivers/clk/imx/clk-imx8qxp-rsrc.c b/drivers/clk/imx/clk-imx8qxp-rsrc.c
new file mode 100644
index 000000000000..ab66811ba9c1
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qxp-rsrc.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#include "clk-scu.h"
+
+/* Keep sorted in the ascending order */
+static u32 imx8qxp_clk_scu_rsrc_table[] = {
+	IMX_SC_R_DC_0_VIDEO0,
+	IMX_SC_R_DC_0_VIDEO1,
+	IMX_SC_R_DC_0,
+	IMX_SC_R_DC_0_PLL_0,
+	IMX_SC_R_DC_0_PLL_1,
+	IMX_SC_R_SPI_0,
+	IMX_SC_R_SPI_1,
+	IMX_SC_R_SPI_2,
+	IMX_SC_R_SPI_3,
+	IMX_SC_R_UART_0,
+	IMX_SC_R_UART_1,
+	IMX_SC_R_UART_2,
+	IMX_SC_R_UART_3,
+	IMX_SC_R_I2C_0,
+	IMX_SC_R_I2C_1,
+	IMX_SC_R_I2C_2,
+	IMX_SC_R_I2C_3,
+	IMX_SC_R_ADC_0,
+	IMX_SC_R_FTM_0,
+	IMX_SC_R_FTM_1,
+	IMX_SC_R_CAN_0,
+	IMX_SC_R_GPU_0_PID0,
+	IMX_SC_R_LCD_0,
+	IMX_SC_R_LCD_0_PWM_0,
+	IMX_SC_R_PWM_0,
+	IMX_SC_R_PWM_1,
+	IMX_SC_R_PWM_2,
+	IMX_SC_R_PWM_3,
+	IMX_SC_R_PWM_4,
+	IMX_SC_R_PWM_5,
+	IMX_SC_R_PWM_6,
+	IMX_SC_R_PWM_7,
+	IMX_SC_R_GPT_0,
+	IMX_SC_R_GPT_1,
+	IMX_SC_R_GPT_2,
+	IMX_SC_R_GPT_3,
+	IMX_SC_R_GPT_4,
+	IMX_SC_R_FSPI_0,
+	IMX_SC_R_FSPI_1,
+	IMX_SC_R_SDHC_0,
+	IMX_SC_R_SDHC_1,
+	IMX_SC_R_SDHC_2,
+	IMX_SC_R_ENET_0,
+	IMX_SC_R_ENET_1,
+	IMX_SC_R_MLB_0,
+	IMX_SC_R_USB_2,
+	IMX_SC_R_NAND,
+	IMX_SC_R_LVDS_0,
+	IMX_SC_R_LVDS_1,
+	IMX_SC_R_M4_0_I2C,
+	IMX_SC_R_ELCDIF_PLL,
+	IMX_SC_R_AUDIO_PLL_0,
+	IMX_SC_R_PI_0,
+	IMX_SC_R_PI_0_PLL,
+	IMX_SC_R_MIPI_0,
+	IMX_SC_R_MIPI_0_PWM_0,
+	IMX_SC_R_MIPI_0_I2C_0,
+	IMX_SC_R_MIPI_0_I2C_1,
+	IMX_SC_R_MIPI_1,
+	IMX_SC_R_MIPI_1_PWM_0,
+	IMX_SC_R_MIPI_1_I2C_0,
+	IMX_SC_R_MIPI_1_I2C_1,
+	IMX_SC_R_CSI_0,
+	IMX_SC_R_CSI_0_PWM_0,
+	IMX_SC_R_CSI_0_I2C_0,
+	IMX_SC_R_AUDIO_PLL_1,
+	IMX_SC_R_AUDIO_CLK_0,
+	IMX_SC_R_AUDIO_CLK_1,
+	IMX_SC_R_A35,
+	IMX_SC_R_VPU_DEC_0,
+	IMX_SC_R_VPU_ENC_0,
+};
+
+const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
+	.rsrc = imx8qxp_clk_scu_rsrc_table,
+	.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
+};
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index d17b418ac577..9e35ae45b3a0 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
 
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -27,9 +28,11 @@ static const char *dc0_sels[] = {
 static int imx8qxp_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *ccm_node = pdev->dev.of_node;
+	const struct imx_clk_scu_rsrc_table *rsrc_table;
 	int ret;
 
-	ret = imx_clk_scu_init(ccm_node);
+	rsrc_table = of_device_get_match_data(&pdev->dev);
+	ret = imx_clk_scu_init(ccm_node, rsrc_table);
 	if (ret)
 		return ret;
 
@@ -130,7 +133,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 
 static const struct of_device_id imx8qxp_match[] = {
 	{ .compatible = "fsl,scu-clk", },
-	{ .compatible = "fsl,imx8qxp-clk", },
+	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index cff0e1bd7030..02044d48d9bc 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  *   Dong Aisheng <aisheng.dong@nxp.com>
  */
 
 #include <dt-bindings/firmware/imx/rsrc.h>
 #include <linux/arm-smccc.h>
+#include <linux/bsearch.h>
 #include <linux/clk-provider.h>
 #include <linux/err.h>
 #include <linux/of_platform.h>
@@ -22,6 +23,7 @@
 static struct imx_sc_ipc *ccm_ipc_handle;
 static struct device_node *pd_np;
 static struct platform_driver imx_clk_scu_driver;
+static const struct imx_clk_scu_rsrc_table *rsrc_table;
 
 struct imx_scu_clk_node {
 	const char *name;
@@ -167,7 +169,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
 	return container_of(hw, struct clk_scu, hw);
 }
 
-int imx_clk_scu_init(struct device_node *np)
+static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
+{
+	return *(u32 *)rsrc - *(u32 *)rsrc_p;
+}
+
+static bool imx_scu_clk_is_valid(u32 rsrc_id)
+{
+	void *p;
+
+	if (!rsrc_table)
+		return true;
+
+	p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
+		    sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
+
+	return p != NULL;
+}
+
+int imx_clk_scu_init(struct device_node *np,
+		     const struct imx_clk_scu_rsrc_table *data)
 {
 	u32 clk_cells;
 	int ret, i;
@@ -186,6 +207,8 @@ int imx_clk_scu_init(struct device_node *np)
 		pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
 		if (!pd_np)
 			return -EINVAL;
+
+		rsrc_table = data;
 	}
 
 	return platform_driver_register(&imx_clk_scu_driver);
@@ -582,6 +605,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
 	struct platform_device *pdev;
 	int ret;
 
+	if (!imx_scu_clk_is_valid(rsrc_id))
+		return ERR_PTR(-EINVAL);
+
 	pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
 	if (!pdev) {
 		pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
@@ -749,6 +775,9 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
 	if (!clk_node)
 		return ERR_PTR(-ENOMEM);
 
+	if (!imx_scu_clk_is_valid(rsrc_id))
+		return ERR_PTR(-EINVAL);
+
 	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
 	if (!clk) {
 		kfree(clk_node);
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index 8ebee0cb0fe6..bcacd8b1d1ab 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  *   Dong Aisheng <aisheng.dong@nxp.com>
  */
 
@@ -14,10 +14,17 @@
 #define IMX_SCU_GPR_CLK_DIV	BIT(1)
 #define IMX_SCU_GPR_CLK_MUX	BIT(2)
 
+struct imx_clk_scu_rsrc_table {
+	const u32 *rsrc;
+	u8 num;
+};
+
 extern struct list_head imx_scu_clks[];
 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
+extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
 
-int imx_clk_scu_init(struct device_node *np);
+int imx_clk_scu_init(struct device_node *np,
+		     const struct imx_clk_scu_rsrc_table *data);
 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
 				      void *data);
 struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
-- 
2.25.1


_______________________________________________
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^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism
  2021-04-23  3:33 ` [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism Dong Aisheng
@ 2021-05-13  7:13   ` Abel Vesa
  2021-05-17  9:48     ` Dong Aisheng
  0 siblings, 1 reply; 20+ messages in thread
From: Abel Vesa @ 2021-05-13  7:13 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-clk, linux-arm-kernel, dongas86, kernel, shawnguo,
	linux-imx, abel.vesa, sboyd

On 21-04-23 11:33:33, Dong Aisheng wrote:
> clk-imx8qxp is a common SCU clock driver used by both QM and QXP

Do you think we should maybe rename it to clk-imx8qdx ?
Might be confusing though. If we leave it like it is, people
will be looking for clk-imx8qm and get frustrated. But then maybe
the same thing would happen with the 8qdx. I have no clue what to
do with the naming here.

Everything else looks OK to me.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> platforms. The clock numbers vary a bit between those two platforms.
> This patch introduces a mechanism to only register the valid clocks
> for one platform by checking the clk resource id table.
> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  drivers/clk/imx/Makefile           |  3 +-
>  drivers/clk/imx/clk-imx8qxp-rsrc.c | 89 ++++++++++++++++++++++++++++++
>  drivers/clk/imx/clk-imx8qxp.c      |  9 ++-
>  drivers/clk/imx/clk-scu.c          | 33 ++++++++++-
>  drivers/clk/imx/clk-scu.h          | 11 +++-
>  5 files changed, 137 insertions(+), 8 deletions(-)
>  create mode 100644 drivers/clk/imx/clk-imx8qxp-rsrc.c
> 
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index dd6a737d060b..2fdd2fff16c7 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
>  obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
>  
>  obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
> -clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
> +clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
> +				     clk-imx8qxp-rsrc.o
>  clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
>  
>  obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
> diff --git a/drivers/clk/imx/clk-imx8qxp-rsrc.c b/drivers/clk/imx/clk-imx8qxp-rsrc.c
> new file mode 100644
> index 000000000000..ab66811ba9c1
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8qxp-rsrc.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#include "clk-scu.h"
> +
> +/* Keep sorted in the ascending order */
> +static u32 imx8qxp_clk_scu_rsrc_table[] = {
> +	IMX_SC_R_DC_0_VIDEO0,
> +	IMX_SC_R_DC_0_VIDEO1,
> +	IMX_SC_R_DC_0,
> +	IMX_SC_R_DC_0_PLL_0,
> +	IMX_SC_R_DC_0_PLL_1,
> +	IMX_SC_R_SPI_0,
> +	IMX_SC_R_SPI_1,
> +	IMX_SC_R_SPI_2,
> +	IMX_SC_R_SPI_3,
> +	IMX_SC_R_UART_0,
> +	IMX_SC_R_UART_1,
> +	IMX_SC_R_UART_2,
> +	IMX_SC_R_UART_3,
> +	IMX_SC_R_I2C_0,
> +	IMX_SC_R_I2C_1,
> +	IMX_SC_R_I2C_2,
> +	IMX_SC_R_I2C_3,
> +	IMX_SC_R_ADC_0,
> +	IMX_SC_R_FTM_0,
> +	IMX_SC_R_FTM_1,
> +	IMX_SC_R_CAN_0,
> +	IMX_SC_R_GPU_0_PID0,
> +	IMX_SC_R_LCD_0,
> +	IMX_SC_R_LCD_0_PWM_0,
> +	IMX_SC_R_PWM_0,
> +	IMX_SC_R_PWM_1,
> +	IMX_SC_R_PWM_2,
> +	IMX_SC_R_PWM_3,
> +	IMX_SC_R_PWM_4,
> +	IMX_SC_R_PWM_5,
> +	IMX_SC_R_PWM_6,
> +	IMX_SC_R_PWM_7,
> +	IMX_SC_R_GPT_0,
> +	IMX_SC_R_GPT_1,
> +	IMX_SC_R_GPT_2,
> +	IMX_SC_R_GPT_3,
> +	IMX_SC_R_GPT_4,
> +	IMX_SC_R_FSPI_0,
> +	IMX_SC_R_FSPI_1,
> +	IMX_SC_R_SDHC_0,
> +	IMX_SC_R_SDHC_1,
> +	IMX_SC_R_SDHC_2,
> +	IMX_SC_R_ENET_0,
> +	IMX_SC_R_ENET_1,
> +	IMX_SC_R_MLB_0,
> +	IMX_SC_R_USB_2,
> +	IMX_SC_R_NAND,
> +	IMX_SC_R_LVDS_0,
> +	IMX_SC_R_LVDS_1,
> +	IMX_SC_R_M4_0_I2C,
> +	IMX_SC_R_ELCDIF_PLL,
> +	IMX_SC_R_AUDIO_PLL_0,
> +	IMX_SC_R_PI_0,
> +	IMX_SC_R_PI_0_PLL,
> +	IMX_SC_R_MIPI_0,
> +	IMX_SC_R_MIPI_0_PWM_0,
> +	IMX_SC_R_MIPI_0_I2C_0,
> +	IMX_SC_R_MIPI_0_I2C_1,
> +	IMX_SC_R_MIPI_1,
> +	IMX_SC_R_MIPI_1_PWM_0,
> +	IMX_SC_R_MIPI_1_I2C_0,
> +	IMX_SC_R_MIPI_1_I2C_1,
> +	IMX_SC_R_CSI_0,
> +	IMX_SC_R_CSI_0_PWM_0,
> +	IMX_SC_R_CSI_0_I2C_0,
> +	IMX_SC_R_AUDIO_PLL_1,
> +	IMX_SC_R_AUDIO_CLK_0,
> +	IMX_SC_R_AUDIO_CLK_1,
> +	IMX_SC_R_A35,
> +	IMX_SC_R_VPU_DEC_0,
> +	IMX_SC_R_VPU_ENC_0,
> +};
> +
> +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
> +	.rsrc = imx8qxp_clk_scu_rsrc_table,
> +	.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
> +};
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index d17b418ac577..9e35ae45b3a0 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018-2021 NXP
>   *	Dong Aisheng <aisheng.dong@nxp.com>
>   */
>  
> @@ -9,6 +9,7 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
>  
> @@ -27,9 +28,11 @@ static const char *dc0_sels[] = {
>  static int imx8qxp_clk_probe(struct platform_device *pdev)
>  {
>  	struct device_node *ccm_node = pdev->dev.of_node;
> +	const struct imx_clk_scu_rsrc_table *rsrc_table;
>  	int ret;
>  
> -	ret = imx_clk_scu_init(ccm_node);
> +	rsrc_table = of_device_get_match_data(&pdev->dev);
> +	ret = imx_clk_scu_init(ccm_node, rsrc_table);
>  	if (ret)
>  		return ret;
>  
> @@ -130,7 +133,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
>  
>  static const struct of_device_id imx8qxp_match[] = {
>  	{ .compatible = "fsl,scu-clk", },
> -	{ .compatible = "fsl,imx8qxp-clk", },
> +	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
>  	{ /* sentinel */ }
>  };
>  
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> index cff0e1bd7030..02044d48d9bc 100644
> --- a/drivers/clk/imx/clk-scu.c
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -1,11 +1,12 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018-2021 NXP
>   *   Dong Aisheng <aisheng.dong@nxp.com>
>   */
>  
>  #include <dt-bindings/firmware/imx/rsrc.h>
>  #include <linux/arm-smccc.h>
> +#include <linux/bsearch.h>
>  #include <linux/clk-provider.h>
>  #include <linux/err.h>
>  #include <linux/of_platform.h>
> @@ -22,6 +23,7 @@
>  static struct imx_sc_ipc *ccm_ipc_handle;
>  static struct device_node *pd_np;
>  static struct platform_driver imx_clk_scu_driver;
> +static const struct imx_clk_scu_rsrc_table *rsrc_table;
>  
>  struct imx_scu_clk_node {
>  	const char *name;
> @@ -167,7 +169,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
>  	return container_of(hw, struct clk_scu, hw);
>  }
>  
> -int imx_clk_scu_init(struct device_node *np)
> +static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
> +{
> +	return *(u32 *)rsrc - *(u32 *)rsrc_p;
> +}
> +
> +static bool imx_scu_clk_is_valid(u32 rsrc_id)
> +{
> +	void *p;
> +
> +	if (!rsrc_table)
> +		return true;
> +
> +	p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
> +		    sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
> +
> +	return p != NULL;
> +}
> +
> +int imx_clk_scu_init(struct device_node *np,
> +		     const struct imx_clk_scu_rsrc_table *data)
>  {
>  	u32 clk_cells;
>  	int ret, i;
> @@ -186,6 +207,8 @@ int imx_clk_scu_init(struct device_node *np)
>  		pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
>  		if (!pd_np)
>  			return -EINVAL;
> +
> +		rsrc_table = data;
>  	}
>  
>  	return platform_driver_register(&imx_clk_scu_driver);
> @@ -582,6 +605,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
>  	struct platform_device *pdev;
>  	int ret;
>  
> +	if (!imx_scu_clk_is_valid(rsrc_id))
> +		return ERR_PTR(-EINVAL);
> +
>  	pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
>  	if (!pdev) {
>  		pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
> @@ -749,6 +775,9 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
>  	if (!clk_node)
>  		return ERR_PTR(-ENOMEM);
>  
> +	if (!imx_scu_clk_is_valid(rsrc_id))
> +		return ERR_PTR(-EINVAL);
> +
>  	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
>  	if (!clk) {
>  		kfree(clk_node);
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> index 8ebee0cb0fe6..bcacd8b1d1ab 100644
> --- a/drivers/clk/imx/clk-scu.h
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
> - * Copyright 2018 NXP
> + * Copyright 2018-2021 NXP
>   *   Dong Aisheng <aisheng.dong@nxp.com>
>   */
>  
> @@ -14,10 +14,17 @@
>  #define IMX_SCU_GPR_CLK_DIV	BIT(1)
>  #define IMX_SCU_GPR_CLK_MUX	BIT(2)
>  
> +struct imx_clk_scu_rsrc_table {
> +	const u32 *rsrc;
> +	u8 num;
> +};
> +
>  extern struct list_head imx_scu_clks[];
>  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
> +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
>  
> -int imx_clk_scu_init(struct device_node *np);
> +int imx_clk_scu_init(struct device_node *np,
> +		     const struct imx_clk_scu_rsrc_table *data);
>  struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
>  				      void *data);
>  struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism
  2021-05-13  7:13   ` Abel Vesa
@ 2021-05-17  9:48     ` Dong Aisheng
  0 siblings, 0 replies; 20+ messages in thread
From: Dong Aisheng @ 2021-05-17  9:48 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Dong Aisheng, linux-clk,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Sascha Hauer, Shawn Guo, dl-linux-imx, Abel Vesa, Stephen Boyd

On Thu, May 13, 2021 at 3:13 PM Abel Vesa <abelvesa@kernel.org> wrote:
>
> On 21-04-23 11:33:33, Dong Aisheng wrote:
> > clk-imx8qxp is a common SCU clock driver used by both QM and QXP
>
> Do you think we should maybe rename it to clk-imx8qdx ?
> Might be confusing though. If we leave it like it is, people
> will be looking for clk-imx8qm and get frustrated. But then maybe
> the same thing would happen with the 8qdx. I have no clue what to
> do with the naming here.
>

Originally I planned to merge clk-imx8qxp.c into clk-scu.c as the
driver itself is
platform independent. But i'm not sure if it's quite necessary as clk-scu keeps
some core libraries.
And for dt platforms, it is common using a previous platform driver on
new platforms.
Anyway, we may consider it in the future.

Regards
Aisheng

> Everything else looks OK to me.
>
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
>
> > platforms. The clock numbers vary a bit between those two platforms.
> > This patch introduces a mechanism to only register the valid clocks
> > for one platform by checking the clk resource id table.
> >
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> >  drivers/clk/imx/Makefile           |  3 +-
> >  drivers/clk/imx/clk-imx8qxp-rsrc.c | 89 ++++++++++++++++++++++++++++++
> >  drivers/clk/imx/clk-imx8qxp.c      |  9 ++-
> >  drivers/clk/imx/clk-scu.c          | 33 ++++++++++-
> >  drivers/clk/imx/clk-scu.h          | 11 +++-
> >  5 files changed, 137 insertions(+), 8 deletions(-)
> >  create mode 100644 drivers/clk/imx/clk-imx8qxp-rsrc.c
> >
> > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> > index dd6a737d060b..2fdd2fff16c7 100644
> > --- a/drivers/clk/imx/Makefile
> > +++ b/drivers/clk/imx/Makefile
> > @@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
> >  obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
> >
> >  obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
> > -clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
> > +clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
> > +                                  clk-imx8qxp-rsrc.o
> >  clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
> >
> >  obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
> > diff --git a/drivers/clk/imx/clk-imx8qxp-rsrc.c b/drivers/clk/imx/clk-imx8qxp-rsrc.c
> > new file mode 100644
> > index 000000000000..ab66811ba9c1
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-imx8qxp-rsrc.c
> > @@ -0,0 +1,89 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + *   Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +#include "clk-scu.h"
> > +
> > +/* Keep sorted in the ascending order */
> > +static u32 imx8qxp_clk_scu_rsrc_table[] = {
> > +     IMX_SC_R_DC_0_VIDEO0,
> > +     IMX_SC_R_DC_0_VIDEO1,
> > +     IMX_SC_R_DC_0,
> > +     IMX_SC_R_DC_0_PLL_0,
> > +     IMX_SC_R_DC_0_PLL_1,
> > +     IMX_SC_R_SPI_0,
> > +     IMX_SC_R_SPI_1,
> > +     IMX_SC_R_SPI_2,
> > +     IMX_SC_R_SPI_3,
> > +     IMX_SC_R_UART_0,
> > +     IMX_SC_R_UART_1,
> > +     IMX_SC_R_UART_2,
> > +     IMX_SC_R_UART_3,
> > +     IMX_SC_R_I2C_0,
> > +     IMX_SC_R_I2C_1,
> > +     IMX_SC_R_I2C_2,
> > +     IMX_SC_R_I2C_3,
> > +     IMX_SC_R_ADC_0,
> > +     IMX_SC_R_FTM_0,
> > +     IMX_SC_R_FTM_1,
> > +     IMX_SC_R_CAN_0,
> > +     IMX_SC_R_GPU_0_PID0,
> > +     IMX_SC_R_LCD_0,
> > +     IMX_SC_R_LCD_0_PWM_0,
> > +     IMX_SC_R_PWM_0,
> > +     IMX_SC_R_PWM_1,
> > +     IMX_SC_R_PWM_2,
> > +     IMX_SC_R_PWM_3,
> > +     IMX_SC_R_PWM_4,
> > +     IMX_SC_R_PWM_5,
> > +     IMX_SC_R_PWM_6,
> > +     IMX_SC_R_PWM_7,
> > +     IMX_SC_R_GPT_0,
> > +     IMX_SC_R_GPT_1,
> > +     IMX_SC_R_GPT_2,
> > +     IMX_SC_R_GPT_3,
> > +     IMX_SC_R_GPT_4,
> > +     IMX_SC_R_FSPI_0,
> > +     IMX_SC_R_FSPI_1,
> > +     IMX_SC_R_SDHC_0,
> > +     IMX_SC_R_SDHC_1,
> > +     IMX_SC_R_SDHC_2,
> > +     IMX_SC_R_ENET_0,
> > +     IMX_SC_R_ENET_1,
> > +     IMX_SC_R_MLB_0,
> > +     IMX_SC_R_USB_2,
> > +     IMX_SC_R_NAND,
> > +     IMX_SC_R_LVDS_0,
> > +     IMX_SC_R_LVDS_1,
> > +     IMX_SC_R_M4_0_I2C,
> > +     IMX_SC_R_ELCDIF_PLL,
> > +     IMX_SC_R_AUDIO_PLL_0,
> > +     IMX_SC_R_PI_0,
> > +     IMX_SC_R_PI_0_PLL,
> > +     IMX_SC_R_MIPI_0,
> > +     IMX_SC_R_MIPI_0_PWM_0,
> > +     IMX_SC_R_MIPI_0_I2C_0,
> > +     IMX_SC_R_MIPI_0_I2C_1,
> > +     IMX_SC_R_MIPI_1,
> > +     IMX_SC_R_MIPI_1_PWM_0,
> > +     IMX_SC_R_MIPI_1_I2C_0,
> > +     IMX_SC_R_MIPI_1_I2C_1,
> > +     IMX_SC_R_CSI_0,
> > +     IMX_SC_R_CSI_0_PWM_0,
> > +     IMX_SC_R_CSI_0_I2C_0,
> > +     IMX_SC_R_AUDIO_PLL_1,
> > +     IMX_SC_R_AUDIO_CLK_0,
> > +     IMX_SC_R_AUDIO_CLK_1,
> > +     IMX_SC_R_A35,
> > +     IMX_SC_R_VPU_DEC_0,
> > +     IMX_SC_R_VPU_ENC_0,
> > +};
> > +
> > +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
> > +     .rsrc = imx8qxp_clk_scu_rsrc_table,
> > +     .num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
> > +};
> > diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> > index d17b418ac577..9e35ae45b3a0 100644
> > --- a/drivers/clk/imx/clk-imx8qxp.c
> > +++ b/drivers/clk/imx/clk-imx8qxp.c
> > @@ -1,6 +1,6 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> > - * Copyright 2018 NXP
> > + * Copyright 2018-2021 NXP
> >   *   Dong Aisheng <aisheng.dong@nxp.com>
> >   */
> >
> > @@ -9,6 +9,7 @@
> >  #include <linux/io.h>
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> > +#include <linux/of_device.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/slab.h>
> >
> > @@ -27,9 +28,11 @@ static const char *dc0_sels[] = {
> >  static int imx8qxp_clk_probe(struct platform_device *pdev)
> >  {
> >       struct device_node *ccm_node = pdev->dev.of_node;
> > +     const struct imx_clk_scu_rsrc_table *rsrc_table;
> >       int ret;
> >
> > -     ret = imx_clk_scu_init(ccm_node);
> > +     rsrc_table = of_device_get_match_data(&pdev->dev);
> > +     ret = imx_clk_scu_init(ccm_node, rsrc_table);
> >       if (ret)
> >               return ret;
> >
> > @@ -130,7 +133,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> >
> >  static const struct of_device_id imx8qxp_match[] = {
> >       { .compatible = "fsl,scu-clk", },
> > -     { .compatible = "fsl,imx8qxp-clk", },
> > +     { .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
> >       { /* sentinel */ }
> >  };
> >
> > diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> > index cff0e1bd7030..02044d48d9bc 100644
> > --- a/drivers/clk/imx/clk-scu.c
> > +++ b/drivers/clk/imx/clk-scu.c
> > @@ -1,11 +1,12 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> > - * Copyright 2018 NXP
> > + * Copyright 2018-2021 NXP
> >   *   Dong Aisheng <aisheng.dong@nxp.com>
> >   */
> >
> >  #include <dt-bindings/firmware/imx/rsrc.h>
> >  #include <linux/arm-smccc.h>
> > +#include <linux/bsearch.h>
> >  #include <linux/clk-provider.h>
> >  #include <linux/err.h>
> >  #include <linux/of_platform.h>
> > @@ -22,6 +23,7 @@
> >  static struct imx_sc_ipc *ccm_ipc_handle;
> >  static struct device_node *pd_np;
> >  static struct platform_driver imx_clk_scu_driver;
> > +static const struct imx_clk_scu_rsrc_table *rsrc_table;
> >
> >  struct imx_scu_clk_node {
> >       const char *name;
> > @@ -167,7 +169,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
> >       return container_of(hw, struct clk_scu, hw);
> >  }
> >
> > -int imx_clk_scu_init(struct device_node *np)
> > +static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
> > +{
> > +     return *(u32 *)rsrc - *(u32 *)rsrc_p;
> > +}
> > +
> > +static bool imx_scu_clk_is_valid(u32 rsrc_id)
> > +{
> > +     void *p;
> > +
> > +     if (!rsrc_table)
> > +             return true;
> > +
> > +     p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
> > +                 sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
> > +
> > +     return p != NULL;
> > +}
> > +
> > +int imx_clk_scu_init(struct device_node *np,
> > +                  const struct imx_clk_scu_rsrc_table *data)
> >  {
> >       u32 clk_cells;
> >       int ret, i;
> > @@ -186,6 +207,8 @@ int imx_clk_scu_init(struct device_node *np)
> >               pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
> >               if (!pd_np)
> >                       return -EINVAL;
> > +
> > +             rsrc_table = data;
> >       }
> >
> >       return platform_driver_register(&imx_clk_scu_driver);
> > @@ -582,6 +605,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
> >       struct platform_device *pdev;
> >       int ret;
> >
> > +     if (!imx_scu_clk_is_valid(rsrc_id))
> > +             return ERR_PTR(-EINVAL);
> > +
> >       pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
> >       if (!pdev) {
> >               pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
> > @@ -749,6 +775,9 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
> >       if (!clk_node)
> >               return ERR_PTR(-ENOMEM);
> >
> > +     if (!imx_scu_clk_is_valid(rsrc_id))
> > +             return ERR_PTR(-EINVAL);
> > +
> >       clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> >       if (!clk) {
> >               kfree(clk_node);
> > diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> > index 8ebee0cb0fe6..bcacd8b1d1ab 100644
> > --- a/drivers/clk/imx/clk-scu.h
> > +++ b/drivers/clk/imx/clk-scu.h
> > @@ -1,6 +1,6 @@
> >  /* SPDX-License-Identifier: GPL-2.0+ */
> >  /*
> > - * Copyright 2018 NXP
> > + * Copyright 2018-2021 NXP
> >   *   Dong Aisheng <aisheng.dong@nxp.com>
> >   */
> >
> > @@ -14,10 +14,17 @@
> >  #define IMX_SCU_GPR_CLK_DIV  BIT(1)
> >  #define IMX_SCU_GPR_CLK_MUX  BIT(2)
> >
> > +struct imx_clk_scu_rsrc_table {
> > +     const u32 *rsrc;
> > +     u8 num;
> > +};
> > +
> >  extern struct list_head imx_scu_clks[];
> >  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
> > +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
> >
> > -int imx_clk_scu_init(struct device_node *np);
> > +int imx_clk_scu_init(struct device_node *np,
> > +                  const struct imx_clk_scu_rsrc_table *data);
> >  struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
> >                                     void *data);
> >  struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
> > --
> > 2.25.1
> >

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
                   ` (3 preceding siblings ...)
  2021-04-23  3:33 ` [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism Dong Aisheng
@ 2021-04-23  3:33 ` Dong Aisheng
  2021-05-13  7:17   ` Abel Vesa
  2021-06-02  1:50   ` Stephen Boyd
  2021-05-03 16:46 ` [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Rob Herring
  2021-05-13  7:18 ` Abel Vesa
  6 siblings, 2 replies; 20+ messages in thread
From: Dong Aisheng @ 2021-04-23  3:33 UTC (permalink / raw)
  To: linux-clk, linux-arm-kernel
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, sboyd, Dong Aisheng

Add imx8qm clock valid resource checking mechanism

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/Makefile          |   2 +-
 drivers/clk/imx/clk-imx8qm-rsrc.c | 116 ++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp.c     |   1 +
 drivers/clk/imx/clk-scu.h         |   1 +
 4 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/imx/clk-imx8qm-rsrc.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 2fdd2fff16c7..c24a2acbfa56 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
 
 obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
 clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
-				     clk-imx8qxp-rsrc.o
+				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
 clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
 
 obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
new file mode 100644
index 000000000000..183a071cbf20
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#include "clk-scu.h"
+
+/* Keep sorted in the ascending order */
+static u32 imx8qm_clk_scu_rsrc_table[] = {
+	IMX_SC_R_A53,
+	IMX_SC_R_A72,
+	IMX_SC_R_DC_0_VIDEO0,
+	IMX_SC_R_DC_0_VIDEO1,
+	IMX_SC_R_DC_0,
+	IMX_SC_R_DC_0_PLL_0,
+	IMX_SC_R_DC_0_PLL_1,
+	IMX_SC_R_DC_1_VIDEO0,
+	IMX_SC_R_DC_1_VIDEO1,
+	IMX_SC_R_DC_1,
+	IMX_SC_R_DC_1_PLL_0,
+	IMX_SC_R_DC_1_PLL_1,
+	IMX_SC_R_SPI_0,
+	IMX_SC_R_SPI_1,
+	IMX_SC_R_SPI_2,
+	IMX_SC_R_SPI_3,
+	IMX_SC_R_UART_0,
+	IMX_SC_R_UART_1,
+	IMX_SC_R_UART_2,
+	IMX_SC_R_UART_3,
+	IMX_SC_R_UART_4,
+	IMX_SC_R_EMVSIM_0,
+	IMX_SC_R_EMVSIM_1,
+	IMX_SC_R_I2C_0,
+	IMX_SC_R_I2C_1,
+	IMX_SC_R_I2C_2,
+	IMX_SC_R_I2C_3,
+	IMX_SC_R_I2C_4,
+	IMX_SC_R_ADC_0,
+	IMX_SC_R_ADC_1,
+	IMX_SC_R_FTM_0,
+	IMX_SC_R_FTM_1,
+	IMX_SC_R_CAN_0,
+	IMX_SC_R_GPU_0_PID0,
+	IMX_SC_R_GPU_1_PID0,
+	IMX_SC_R_PWM_0,
+	IMX_SC_R_PWM_1,
+	IMX_SC_R_PWM_2,
+	IMX_SC_R_PWM_3,
+	IMX_SC_R_PWM_4,
+	IMX_SC_R_PWM_5,
+	IMX_SC_R_PWM_6,
+	IMX_SC_R_PWM_7,
+	IMX_SC_R_GPT_0,
+	IMX_SC_R_GPT_1,
+	IMX_SC_R_GPT_2,
+	IMX_SC_R_GPT_3,
+	IMX_SC_R_GPT_4,
+	IMX_SC_R_FSPI_0,
+	IMX_SC_R_FSPI_1,
+	IMX_SC_R_SDHC_0,
+	IMX_SC_R_SDHC_1,
+	IMX_SC_R_SDHC_2,
+	IMX_SC_R_ENET_0,
+	IMX_SC_R_ENET_1,
+	IMX_SC_R_MLB_0,
+	IMX_SC_R_USB_2,
+	IMX_SC_R_NAND,
+	IMX_SC_R_LVDS_0,
+	IMX_SC_R_LVDS_0_PWM_0,
+	IMX_SC_R_LVDS_0_I2C_0,
+	IMX_SC_R_LVDS_0_I2C_1,
+	IMX_SC_R_LVDS_1,
+	IMX_SC_R_LVDS_1_PWM_0,
+	IMX_SC_R_LVDS_1_I2C_0,
+	IMX_SC_R_LVDS_1_I2C_1,
+	IMX_SC_R_M4_0_I2C,
+	IMX_SC_R_M4_1_I2C,
+	IMX_SC_R_AUDIO_PLL_0,
+	IMX_SC_R_VPU_UART,
+	IMX_SC_R_VPUCORE,
+	IMX_SC_R_MIPI_0,
+	IMX_SC_R_MIPI_0_PWM_0,
+	IMX_SC_R_MIPI_0_I2C_0,
+	IMX_SC_R_MIPI_0_I2C_1,
+	IMX_SC_R_MIPI_1,
+	IMX_SC_R_MIPI_1_PWM_0,
+	IMX_SC_R_MIPI_1_I2C_0,
+	IMX_SC_R_MIPI_1_I2C_1,
+	IMX_SC_R_CSI_0,
+	IMX_SC_R_CSI_0_PWM_0,
+	IMX_SC_R_CSI_0_I2C_0,
+	IMX_SC_R_CSI_1,
+	IMX_SC_R_CSI_1_PWM_0,
+	IMX_SC_R_CSI_1_I2C_0,
+	IMX_SC_R_HDMI,
+	IMX_SC_R_HDMI_I2S,
+	IMX_SC_R_HDMI_I2C_0,
+	IMX_SC_R_HDMI_PLL_0,
+	IMX_SC_R_HDMI_RX,
+	IMX_SC_R_HDMI_RX_BYPASS,
+	IMX_SC_R_HDMI_RX_I2C_0,
+	IMX_SC_R_AUDIO_PLL_1,
+	IMX_SC_R_AUDIO_CLK_0,
+	IMX_SC_R_AUDIO_CLK_1,
+	IMX_SC_R_HDMI_RX_PWM_0,
+	IMX_SC_R_HDMI_PLL_1,
+	IMX_SC_R_VPU,
+};
+
+const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
+	.rsrc = imx8qm_clk_scu_rsrc_table,
+	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
+};
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 9e35ae45b3a0..88cc737ee125 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -134,6 +134,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 static const struct of_device_id imx8qxp_match[] = {
 	{ .compatible = "fsl,scu-clk", },
 	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
+	{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index bcacd8b1d1ab..22156e93b85d 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -22,6 +22,7 @@ struct imx_clk_scu_rsrc_table {
 extern struct list_head imx_scu_clks[];
 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
+extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
 
 int imx_clk_scu_init(struct device_node *np,
 		     const struct imx_clk_scu_rsrc_table *data);
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-04-23  3:33 ` [PATCH 6/6] clk: imx8qm: add clock valid resource checking Dong Aisheng
@ 2021-05-13  7:17   ` Abel Vesa
  2021-06-02  1:50   ` Stephen Boyd
  1 sibling, 0 replies; 20+ messages in thread
From: Abel Vesa @ 2021-05-13  7:17 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-clk, linux-arm-kernel, dongas86, kernel, shawnguo,
	linux-imx, abel.vesa, sboyd

On 21-04-23 11:33:34, Dong Aisheng wrote:
> Add imx8qm clock valid resource checking mechanism
> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/Makefile          |   2 +-
>  drivers/clk/imx/clk-imx8qm-rsrc.c | 116 ++++++++++++++++++++++++++++++
>  drivers/clk/imx/clk-imx8qxp.c     |   1 +
>  drivers/clk/imx/clk-scu.h         |   1 +
>  4 files changed, 119 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/imx/clk-imx8qm-rsrc.c
> 
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 2fdd2fff16c7..c24a2acbfa56 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
>  
>  obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
>  clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
> -				     clk-imx8qxp-rsrc.o
> +				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
>  clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
>  
>  obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o
> diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> new file mode 100644
> index 000000000000..183a071cbf20
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#include "clk-scu.h"
> +
> +/* Keep sorted in the ascending order */
> +static u32 imx8qm_clk_scu_rsrc_table[] = {
> +	IMX_SC_R_A53,
> +	IMX_SC_R_A72,
> +	IMX_SC_R_DC_0_VIDEO0,
> +	IMX_SC_R_DC_0_VIDEO1,
> +	IMX_SC_R_DC_0,
> +	IMX_SC_R_DC_0_PLL_0,
> +	IMX_SC_R_DC_0_PLL_1,
> +	IMX_SC_R_DC_1_VIDEO0,
> +	IMX_SC_R_DC_1_VIDEO1,
> +	IMX_SC_R_DC_1,
> +	IMX_SC_R_DC_1_PLL_0,
> +	IMX_SC_R_DC_1_PLL_1,
> +	IMX_SC_R_SPI_0,
> +	IMX_SC_R_SPI_1,
> +	IMX_SC_R_SPI_2,
> +	IMX_SC_R_SPI_3,
> +	IMX_SC_R_UART_0,
> +	IMX_SC_R_UART_1,
> +	IMX_SC_R_UART_2,
> +	IMX_SC_R_UART_3,
> +	IMX_SC_R_UART_4,
> +	IMX_SC_R_EMVSIM_0,
> +	IMX_SC_R_EMVSIM_1,
> +	IMX_SC_R_I2C_0,
> +	IMX_SC_R_I2C_1,
> +	IMX_SC_R_I2C_2,
> +	IMX_SC_R_I2C_3,
> +	IMX_SC_R_I2C_4,
> +	IMX_SC_R_ADC_0,
> +	IMX_SC_R_ADC_1,
> +	IMX_SC_R_FTM_0,
> +	IMX_SC_R_FTM_1,
> +	IMX_SC_R_CAN_0,
> +	IMX_SC_R_GPU_0_PID0,
> +	IMX_SC_R_GPU_1_PID0,
> +	IMX_SC_R_PWM_0,
> +	IMX_SC_R_PWM_1,
> +	IMX_SC_R_PWM_2,
> +	IMX_SC_R_PWM_3,
> +	IMX_SC_R_PWM_4,
> +	IMX_SC_R_PWM_5,
> +	IMX_SC_R_PWM_6,
> +	IMX_SC_R_PWM_7,
> +	IMX_SC_R_GPT_0,
> +	IMX_SC_R_GPT_1,
> +	IMX_SC_R_GPT_2,
> +	IMX_SC_R_GPT_3,
> +	IMX_SC_R_GPT_4,
> +	IMX_SC_R_FSPI_0,
> +	IMX_SC_R_FSPI_1,
> +	IMX_SC_R_SDHC_0,
> +	IMX_SC_R_SDHC_1,
> +	IMX_SC_R_SDHC_2,
> +	IMX_SC_R_ENET_0,
> +	IMX_SC_R_ENET_1,
> +	IMX_SC_R_MLB_0,
> +	IMX_SC_R_USB_2,
> +	IMX_SC_R_NAND,
> +	IMX_SC_R_LVDS_0,
> +	IMX_SC_R_LVDS_0_PWM_0,
> +	IMX_SC_R_LVDS_0_I2C_0,
> +	IMX_SC_R_LVDS_0_I2C_1,
> +	IMX_SC_R_LVDS_1,
> +	IMX_SC_R_LVDS_1_PWM_0,
> +	IMX_SC_R_LVDS_1_I2C_0,
> +	IMX_SC_R_LVDS_1_I2C_1,
> +	IMX_SC_R_M4_0_I2C,
> +	IMX_SC_R_M4_1_I2C,
> +	IMX_SC_R_AUDIO_PLL_0,
> +	IMX_SC_R_VPU_UART,
> +	IMX_SC_R_VPUCORE,
> +	IMX_SC_R_MIPI_0,
> +	IMX_SC_R_MIPI_0_PWM_0,
> +	IMX_SC_R_MIPI_0_I2C_0,
> +	IMX_SC_R_MIPI_0_I2C_1,
> +	IMX_SC_R_MIPI_1,
> +	IMX_SC_R_MIPI_1_PWM_0,
> +	IMX_SC_R_MIPI_1_I2C_0,
> +	IMX_SC_R_MIPI_1_I2C_1,
> +	IMX_SC_R_CSI_0,
> +	IMX_SC_R_CSI_0_PWM_0,
> +	IMX_SC_R_CSI_0_I2C_0,
> +	IMX_SC_R_CSI_1,
> +	IMX_SC_R_CSI_1_PWM_0,
> +	IMX_SC_R_CSI_1_I2C_0,
> +	IMX_SC_R_HDMI,
> +	IMX_SC_R_HDMI_I2S,
> +	IMX_SC_R_HDMI_I2C_0,
> +	IMX_SC_R_HDMI_PLL_0,
> +	IMX_SC_R_HDMI_RX,
> +	IMX_SC_R_HDMI_RX_BYPASS,
> +	IMX_SC_R_HDMI_RX_I2C_0,
> +	IMX_SC_R_AUDIO_PLL_1,
> +	IMX_SC_R_AUDIO_CLK_0,
> +	IMX_SC_R_AUDIO_CLK_1,
> +	IMX_SC_R_HDMI_RX_PWM_0,
> +	IMX_SC_R_HDMI_PLL_1,
> +	IMX_SC_R_VPU,
> +};
> +
> +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
> +	.rsrc = imx8qm_clk_scu_rsrc_table,
> +	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
> +};
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 9e35ae45b3a0..88cc737ee125 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -134,6 +134,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
>  static const struct of_device_id imx8qxp_match[] = {
>  	{ .compatible = "fsl,scu-clk", },
>  	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
> +	{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
>  	{ /* sentinel */ }
>  };
>  
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> index bcacd8b1d1ab..22156e93b85d 100644
> --- a/drivers/clk/imx/clk-scu.h
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -22,6 +22,7 @@ struct imx_clk_scu_rsrc_table {
>  extern struct list_head imx_scu_clks[];
>  extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
>  extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
> +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
>  
>  int imx_clk_scu_init(struct device_node *np,
>  		     const struct imx_clk_scu_rsrc_table *data);
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-04-23  3:33 ` [PATCH 6/6] clk: imx8qm: add clock valid resource checking Dong Aisheng
  2021-05-13  7:17   ` Abel Vesa
@ 2021-06-02  1:50   ` Stephen Boyd
  2021-06-04  6:46     ` Abel Vesa
  1 sibling, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2021-06-02  1:50 UTC (permalink / raw)
  To: Dong Aisheng, linux-arm-kernel, linux-clk
  Cc: dongas86, kernel, shawnguo, linux-imx, abel.vesa, Dong Aisheng

Quoting Dong Aisheng (2021-04-22 20:33:34)
> diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> new file mode 100644
> index 000000000000..183a071cbf20
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + *     Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#include "clk-scu.h"
> +
> +/* Keep sorted in the ascending order */
> +static u32 imx8qm_clk_scu_rsrc_table[] = {

const?

> +       IMX_SC_R_A53,

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-06-02  1:50   ` Stephen Boyd
@ 2021-06-04  6:46     ` Abel Vesa
  2021-06-04  7:04       ` Dong Aisheng
  0 siblings, 1 reply; 20+ messages in thread
From: Abel Vesa @ 2021-06-04  6:46 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Dong Aisheng, linux-arm-kernel, linux-clk, dongas86, kernel,
	shawnguo, linux-imx

On 21-06-01 18:50:06, Stephen Boyd wrote:
> Quoting Dong Aisheng (2021-04-22 20:33:34)
> > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > new file mode 100644
> > index 000000000000..183a071cbf20
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > @@ -0,0 +1,116 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +#include "clk-scu.h"
> > +
> > +/* Keep sorted in the ascending order */
> > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> 
> const?
> 

Aisheng, no need to resend, I'll fold that in.

> > +       IMX_SC_R_A53,

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-06-04  6:46     ` Abel Vesa
@ 2021-06-04  7:04       ` Dong Aisheng
  2021-06-04  8:20         ` Abel Vesa
  0 siblings, 1 reply; 20+ messages in thread
From: Dong Aisheng @ 2021-06-04  7:04 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Stephen Boyd, Dong Aisheng,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	linux-clk, Sascha Hauer, Shawn Guo, dl-linux-imx

On Fri, Jun 4, 2021 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> On 21-06-01 18:50:06, Stephen Boyd wrote:
> > Quoting Dong Aisheng (2021-04-22 20:33:34)
> > > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > new file mode 100644
> > > index 000000000000..183a071cbf20
> > > --- /dev/null
> > > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > @@ -0,0 +1,116 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019-2021 NXP
> > > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > > + */
> > > +
> > > +#include <dt-bindings/firmware/imx/rsrc.h>
> > > +
> > > +#include "clk-scu.h"
> > > +
> > > +/* Keep sorted in the ascending order */
> > > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> >
> > const?

Stephen,
Thanks for pointing this out

> >
>
> Aisheng, no need to resend, I'll fold that in.

Thanks

Regards
Aisheng

>
> > > +       IMX_SC_R_A53,

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 6/6] clk: imx8qm: add clock valid resource checking
  2021-06-04  7:04       ` Dong Aisheng
@ 2021-06-04  8:20         ` Abel Vesa
  0 siblings, 0 replies; 20+ messages in thread
From: Abel Vesa @ 2021-06-04  8:20 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Stephen Boyd, Dong Aisheng,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	linux-clk, Sascha Hauer, Shawn Guo, dl-linux-imx

On 21-06-04 15:04:03, Dong Aisheng wrote:
> On Fri, Jun 4, 2021 at 2:46 PM Abel Vesa <abel.vesa@nxp.com> wrote:
> >
> > On 21-06-01 18:50:06, Stephen Boyd wrote:
> > > Quoting Dong Aisheng (2021-04-22 20:33:34)
> > > > diff --git a/drivers/clk/imx/clk-imx8qm-rsrc.c b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > > new file mode 100644
> > > > index 000000000000..183a071cbf20
> > > > --- /dev/null
> > > > +++ b/drivers/clk/imx/clk-imx8qm-rsrc.c
> > > > @@ -0,0 +1,116 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2019-2021 NXP
> > > > + *     Dong Aisheng <aisheng.dong@nxp.com>
> > > > + */
> > > > +
> > > > +#include <dt-bindings/firmware/imx/rsrc.h>
> > > > +
> > > > +#include "clk-scu.h"
> > > > +
> > > > +/* Keep sorted in the ascending order */
> > > > +static u32 imx8qm_clk_scu_rsrc_table[] = {
> > >
> > > const?
> 
> Stephen,
> Thanks for pointing this out
> 
> > >
> >
> > Aisheng, no need to resend, I'll fold that in.
> 
> Thanks
> 

Applied all and folded the const change in.

Thanks.

> Regards
> Aisheng
> 
> >
> > > > +       IMX_SC_R_A53,

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
                   ` (4 preceding siblings ...)
  2021-04-23  3:33 ` [PATCH 6/6] clk: imx8qm: add clock valid resource checking Dong Aisheng
@ 2021-05-03 16:46 ` Rob Herring
  2021-05-13  7:18 ` Abel Vesa
  6 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-05-03 16:46 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: devicetree, abel.vesa, sboyd, linux-clk, linux-arm-kernel,
	kernel, shawnguo, linux-imx, dongas86

On Fri, 23 Apr 2021 11:33:29 +0800, Dong Aisheng wrote:
> There is a typo in binding doc that the name of compatible string of
> scu clock should be "fsl,xxx-clk" rather than "fsl,xxx-clock".
> In reality, both example and dts using "fsl,xxx-clk", so fixing the doc
> is enough.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
  2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
                   ` (5 preceding siblings ...)
  2021-05-03 16:46 ` [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Rob Herring
@ 2021-05-13  7:18 ` Abel Vesa
  6 siblings, 0 replies; 20+ messages in thread
From: Abel Vesa @ 2021-05-13  7:18 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-clk, linux-arm-kernel, dongas86, kernel, shawnguo,
	linux-imx, abel.vesa, sboyd, devicetree

On 21-04-23 11:33:29, Dong Aisheng wrote:
> There is a typo in binding doc that the name of compatible string of
> scu clock should be "fsl,xxx-clk" rather than "fsl,xxx-clock".
> In reality, both example and dts using "fsl,xxx-clk", so fixing the doc
> is enough.
> 
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> index 395359dc94fd..3adf3f6f2beb 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> @@ -86,8 +86,8 @@ This binding uses the common clock binding[1].
>  
>  Required properties:
>  - compatible:		Should be one of:
> -			  "fsl,imx8qm-clock"
> -			  "fsl,imx8qxp-clock"
> +			  "fsl,imx8qm-clk"
> +			  "fsl,imx8qxp-clk"
>  			followed by "fsl,scu-clk"
>  - #clock-cells:		Should be either
>  			2: Contains the Resource and Clock ID value.
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 20+ messages in thread

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2021-04-23  3:33 [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Dong Aisheng
2021-04-23  3:33 ` [PATCH 2/6] dt-bindings: arm: imx: scu: drop deprecated legacy clock binding Dong Aisheng
2021-05-03 16:47   ` Rob Herring
2021-04-23  3:33 ` [PATCH 3/6] clk: imx: scu: remove legacy scu clock binding support Dong Aisheng
2021-05-13 20:04   ` Abel Vesa
2021-04-23  3:33 ` [PATCH 4/6] clk: imx: scu: add gpr clocks support Dong Aisheng
2021-05-13  6:58   ` Abel Vesa
2021-05-17  9:49     ` Dong Aisheng
2021-05-17  9:52       ` Abel Vesa
2021-04-23  3:33 ` [PATCH 5/6] clk: imx8qxp: add clock valid checking mechnism Dong Aisheng
2021-05-13  7:13   ` Abel Vesa
2021-05-17  9:48     ` Dong Aisheng
2021-04-23  3:33 ` [PATCH 6/6] clk: imx8qm: add clock valid resource checking Dong Aisheng
2021-05-13  7:17   ` Abel Vesa
2021-06-02  1:50   ` Stephen Boyd
2021-06-04  6:46     ` Abel Vesa
2021-06-04  7:04       ` Dong Aisheng
2021-06-04  8:20         ` Abel Vesa
2021-05-03 16:46 ` [PATCH 1/6] dt-bindings: arm: imx: scu: fix naming typo of clk compatible string Rob Herring
2021-05-13  7:18 ` Abel Vesa

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