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From: Abel Vesa <abel.vesa@nxp.com>
To: Dong Aisheng <aisheng.dong@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org, dongas86@gmail.com,
	linux-imx@nxp.com, shawnguo@kernel.org, kernel@pengutronix.de,
	festevam@gmail.com, devicetree@vger.kernel.org,
	Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks
Date: Wed, 26 May 2021 13:34:19 +0300	[thread overview]
Message-ID: <YK4kK+r2Dkb+J+CH@ryzen.lan> (raw)
In-Reply-To: <20210521031248.2763667-2-aisheng.dong@nxp.com>

On 21-05-21 11:12:47, Dong Aisheng wrote:
> enet tx clk actually is sourced from a gpr divider, not default enet
> clk. Add enet grp clocks for user to use correctly.
> 
> Cc: Abel Vesa <abel.vesa@nxp.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

I'm OK with this:

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8qxp.c | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 88cc737ee125..f3cdd6449212 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -25,6 +25,16 @@ static const char *dc0_sels[] = {
>  	"dc0_bypass0_clk",
>  };
>  
> +static const char *enet0_rgmii_txc_sels[] = {
> +	"enet0_ref_div",
> +	"dummy",
> +};
> +
> +static const char *enet1_rgmii_txc_sels[] = {
> +	"enet1_ref_div",
> +	"dummy",
> +};
> +
>  static int imx8qxp_clk_probe(struct platform_device *pdev)
>  {
>  	struct device_node *ccm_node = pdev->dev.of_node;
> @@ -80,12 +90,16 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
>  	imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
> -	imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
> +	imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
> +	imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
>  	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
> -	imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> -	imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
> +	imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
> +	imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
>  	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
> -	imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
> +	imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
>  	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
>  	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
>  	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
> -- 
> 2.25.1
> 

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  reply	other threads:[~2021-05-26 12:53 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-21  3:12 [PATCH 0/2] arm64: imx8: fix booting with lastest nxp flash.bin Dong Aisheng
2021-05-21  3:12 ` [PATCH 1/2] clk: imx: scu: add enet rgmii gpr clocks Dong Aisheng
2021-05-26 10:34   ` Abel Vesa [this message]
2021-05-26 10:46     ` Abel Vesa
2021-05-21  3:12 ` [PATCH 2/2] arm64: dts: imx8: conn: fix enet clock setting Dong Aisheng
2021-05-23  5:34   ` Shawn Guo

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