From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E87D1C47093 for ; Wed, 2 Jun 2021 09:29:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8325613B4 for ; Wed, 2 Jun 2021 09:29:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8325613B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oAzZt3WUcLbg3hUWS1QuBXj0fG2uAkl8dhzZEY30LII=; b=fQvEStW/mh/4Ng n3SDGDgOs2K5lGh4CLxGFTRRWZ0x3YGvgPBih7kIerjd2L8I9Nce+L1OEFr1C3p8kcaKPVUXxYS94 UkyYJPjzX0cAjKzALJiGIM8ToiIUbiUT6HALyB6wd0/KL9O6zxKZXSXcHazmKQILbUaIJk8fCmTH7 QsRGAYO0Ptd9hrhKows8M4Pox5lPB1Wa7/2rNPIQALQfJ1gRyDdQQ9PCZrPck0eThnC+5C1IWs/Kq JbtAeYp9S62FyYTVPI9MI2AgJ1lMJkEJkavbW2pvBi06m01iQqXUuNilst1FvHMED53usN3XLDpxq NVDddZQAXuQysUEbw28w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loNAc-002yCX-3N; Wed, 02 Jun 2021 09:28:14 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loNAZ-002yBK-Cm for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 09:28:12 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id D0BED8027; Wed, 2 Jun 2021 09:28:16 +0000 (UTC) Date: Wed, 2 Jun 2021 12:28:06 +0300 From: Tony Lindgren To: Sven Peter Cc: Rob Herring , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> <6052f2f1-1e3f-474e-a767-e08ca19fbd43@www.fastmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <6052f2f1-1e3f-474e-a767-e08ca19fbd43@www.fastmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_022811_496288_72B2B2AC X-CRM114-Status: GOOD ( 10.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Sven Peter [210530 11:11]: > The problem with that approach is that to enable e.g. UART_0 we actually need > to enable its parents as well, e.g. the Apple Device Tree for the M1 has the > following clock topology: > > UART0 (0x23b700270), parent: UART_P > UART_P (0x23b700220), parent: SIO > SIO (0x23b7001c0), parent: n/a > > The offsets and the parent/child relationship for all of these three clocks > change between SoCs. If I now use the offset as the clock id I still need > to specify that if e.g. UART uses <&clk_controller 0x270> I first need > to enable 0x1c0 and then 0x220 and only then 0x270. Maybe take a look what I suggested on using assigned-clocks and related properties in the clock controller node. That might solve the issue in a generic way for other SoCs too. Regards, Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel