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Mon, 21 Jun 2021 07:09:58 -0700 (PDT) Date: Mon, 21 Jun 2021 16:11:55 +0200 From: Thierry Reding To: Krzysztof Kozlowski Cc: Rob Herring , Will Deacon , Joerg Roedel , Linux IOMMU , Jon Hunter , Nicolin Chen , linux-tegra , Robin Murphy , linux-arm-kernel Subject: Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string Message-ID: References: <20210603164632.1000458-1-thierry.reding@gmail.com> <20210603164632.1000458-3-thierry.reding@gmail.com> <14551e79-853d-471f-bb5e-0d2d6581a9b6@canonical.com> MIME-Version: 1.0 In-Reply-To: <14551e79-853d-471f-bb5e-0d2d6581a9b6@canonical.com> User-Agent: Mutt/2.0.7 (481f3800) (2021-05-04) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210621_071005_104314_EADC7622 X-CRM114-Status: GOOD ( 35.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============3315820317836612192==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============3315820317836612192== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Ug2yoxoaj18CzXNu" Content-Disposition: inline --Ug2yoxoaj18CzXNu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 21, 2021 at 08:46:54AM +0200, Krzysztof Kozlowski wrote: > On 18/06/2021 21:47, Rob Herring wrote: > > On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding wrote: > >> > >> From: Thierry Reding > >> > >> The ARM SMMU instantiations found on Tegra186 and later need inter- > >> operation with the memory controller in order to correctly program > >> stream ID overrides. > >> > >> Furthermore, on Tegra194 multiple instances of the SMMU can gang up > >> to achieve higher throughput. In order to do this, they have to be > >> programmed identically so that the memory controller can interleave > >> memory accesses between them. > >> > >> Add the Tegra186 compatible string to make sure the interoperation > >> with the memory controller can be enabled on that SoC generation. > >> > >> Signed-off-by: Thierry Reding > >> --- > >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++-- > >> 1 file changed, 9 insertions(+), 2 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/D= ocumentation/devicetree/bindings/iommu/arm,smmu.yaml > >> index 9d27aa5111d4..1181b590db71 100644 > >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > >> @@ -54,8 +54,14 @@ properties: > >> - const: arm,mmu-500 > >> - description: NVIDIA SoCs that program two ARM MMU-500s identi= cally > >> items: > >> + - description: NVIDIA SoCs that require memory controller inter= action > >=20 > > This is not valid jsonschema: > >=20 > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm= ,smmu.yaml: > > properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one > > must be fixed: > > None is not of type 'object', 'boolean' > > None is not of type 'array' > > from schema $id: http://json-schema.org/draft-07/schema# > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm= ,smmu.yaml: > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one > > must be fixed: > > None is not of type 'object' > > None is not of type 'array' > > from schema $id: http://devicetree.org/meta-schemas/keywords.yaml# > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm= ,smmu.yaml: > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one > > must be fixed: > > None is not of type 'object' > > None is not of type 'array' > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml# > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm= ,smmu.yaml: > > properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one > > must be fixed: > > [{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const': > > 'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of > > type 'object' > > {'const': 'nvidia,tegra194-smmu'} is not of type 'string' > > {'const': 'nvidia,tegra186-smmu'} is not of type 'string' > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml# > >=20 > >=20 > > This was not reviewed nor tested since the DT list was not Cc'ed. >=20 > Ugh, I see now weird empty item on a list... and not only DT list was > skipped - Thierry did not Cc you either. This seemed like a too trivial addition to waste Rob's time on, so I didn't add him (or the DT list for that matter) on Cc. The ARM SMMU maintainers had reviewed this, which seemed like it was enough for what the DT bindings change was doing. In any case, I clearly should've checked the DT binding check output more carefully. It's rather messy for Tegra because there's quite a few that we haven't converted yet. I'll have to resume my effort to convert the remaining ones and fixup the device trees so that we can actually run the DT binding and DTB validation checks more usefully. > My bad, I did not check that patch thoroughly before applying. >=20 > Thierry, please Cc folks mentioned by get_maintainer.pl. Either sent a > fix or a revert, if fix needs more time. I've sent out a follow-up fix that removes the two bogus lines. It looks like that was the result of a bad conflict resolution on my part. > Additionally, why the patch changes reg to "minItems: 1" for > nvidia,tegra194-smmu? This is because originally the Tegra194 SMMU nodes were supposed to only represent a "dual" instance. However, on Tegra194 there are three SMMU instances in total, with the third instance (dedicated for isochronous traffic) being completely separate and having only a single range of registers. That third instance was previously supposed to be covered by the normal "arm,mmu-500" compatible string, but given that we really need that interoperation between SMMU and memory controller for SID override programming, we need the Tegra-specific compatible for the ISO instance of the SMMU as well. And since that uses only one set of registers, minItems had to become 1. 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