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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id c20sm1747132ots.50.2022.01.20.09.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 09:09:17 -0800 (PST) Received: (nullmailer pid 1607218 invoked by uid 1000); Thu, 20 Jan 2022 17:09:17 -0000 Date: Thu, 20 Jan 2022 11:09:17 -0600 From: Rob Herring To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Thomas Petazzoni , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Marek =?iso-8859-1?Q?Beh=FAn?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 05/11] PCI: mvebu: Correctly configure x1/x4 mode Message-ID: References: <20220105150239.9628-1-pali@kernel.org> <20220112151814.24361-1-pali@kernel.org> <20220112151814.24361-6-pali@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220112151814.24361-6-pali@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220120_090919_672313_203CD2A7 X-CRM114-Status: GOOD ( 24.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 12, 2022 at 04:18:08PM +0100, Pali Roh=E1r wrote: > If x1/x4 mode is not set correctly then link with endpoint card is not > established. > = > Use DTS property 'num-lanes' to deteriminate x1/x4 mode. > = > Signed-off-by: Pali Roh=E1r > --- > drivers/pci/controller/pci-mvebu.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > = > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/= pci-mvebu.c > index a075ba26cff1..0f2ec0a17874 100644 > --- a/drivers/pci/controller/pci-mvebu.c > +++ b/drivers/pci/controller/pci-mvebu.c > @@ -93,6 +93,7 @@ struct mvebu_pcie_port { > void __iomem *base; > u32 port; > u32 lane; > + bool is_x4; I would just store the number of lanes. > int devfn; > unsigned int mem_target; > unsigned int mem_attr; > @@ -233,13 +234,25 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie= _port *port) > = > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > { > - u32 ctrl, cmd, dev_rev, mask; > + u32 ctrl, lnkcap, cmd, dev_rev, mask; > = > /* Setup PCIe controller to Root Complex mode. */ > ctrl =3D mvebu_readl(port, PCIE_CTRL_OFF); > ctrl |=3D PCIE_CTRL_RC_MODE; > mvebu_writel(port, ctrl, PCIE_CTRL_OFF); > = > + /* > + * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link > + * Capability register. This register is defined by PCIe specification > + * as read-only but this mvebu controller has it as read-write and must > + * be set to number of SerDes PCIe lanes (1 or 4). If this register is > + * not set correctly then link with endpoint card is not established. > + */ > + lnkcap =3D mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); > + lnkcap &=3D ~PCI_EXP_LNKCAP_MLW; > + lnkcap |=3D (port->is_x4 ? 4 : 1) << 4; then this is just: lanes << 4 > + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); > + > /* Disable Root Bridge I/O space, memory space and bus mastering. */ > cmd =3D mvebu_readl(port, PCIE_CMD_OFF); > cmd &=3D ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); > @@ -986,6 +999,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *p= cie, > struct device *dev =3D &pcie->pdev->dev; > enum of_gpio_flags flags; > int reset_gpio, ret; > + u32 num_lanes; > = > port->pcie =3D pcie; > = > @@ -998,6 +1012,9 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *= pcie, > if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) > port->lane =3D 0; > = > + if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes = =3D=3D 4) > + port->is_x4 =3D true; And this can be: num_lanes =3D 1; of_property_read_u32(child, "num-lanes", &num_lanes); If you want to validate the DT is only 1 or 4, make the DT schema do = that. > + > port->name =3D devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, > port->lane); > if (!port->name) { > -- = > 2.20.1 > = > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel