From: Rob Herring <robh@kernel.org>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: krzysztof.kozlowski+dt@linaro.org, chunkuang.hu@kernel.org,
p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com,
jason-jh.lin@mediatek.com, nancy.lin@mediatek.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 3/5] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
Date: Tue, 26 Apr 2022 15:25:15 -0500 [thread overview]
Message-ID: <YmhVKw/FQ/iQfLLD@robh.at.kernel.org> (raw)
In-Reply-To: <20220419033237.23405-4-rex-bc.chen@mediatek.com>
On Tue, Apr 19, 2022 at 11:32:35AM +0800, Rex-BC Chen wrote:
> From: "Nancy.Lin" <nancy.lin@mediatek.com>
>
> Add vdosys1 RDMA definition.
How does this compare to the mediatek,mt8183-mdp3-rdma or
mediatek,mt8195-disp-rdma?
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++
> 1 file changed, 86 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> new file mode 100644
> index 000000000000..6ab773569462
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MDP RDMA
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> + The mediatek MDP RDMA stands for Read Direct Memory Access.
> + It provides real time data to the back-end panel driver, such as DSI,
> + DPI and DP_INTF.
> + It contains one line buffer to store the sufficient pixel data.
> + RDMA device node must be siblings to the central MMSYS_CONFIG node.
> + For a description of the MMSYS_CONFIG binding, see
> + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: mediatek,mt8195-vdo1-rdma
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + description: A phandle and PM domain specifier as defined by bindings of
> + the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> + clocks:
> + items:
> + - description: RDMA Clock
> +
> + iommus:
> + description:
> + This property should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> + mediatek,gce-client-reg:
> + description:
> + The register of display function block to be set by gce. There are 4 arguments,
> + such as gce node, subsys id, offset and register size. The subsys id that is
> + mapping to the register of display function blocks is defined in the gce header
> + include/include/dt-bindings/gce/<chip>-gce.h of each chips.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> + - clocks
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> + #include <dt-bindings/gce/mt8195-gce.h>
> + #include <dt-bindings/memory/mt8195-memory-port.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + vdo1_rdma0: mdp-rdma@1c104000 {
> + compatible = "mediatek,mt8195-vdo1-rdma";
> + reg = <0 0x1c104000 0 0x1000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
> + };
> + };
> --
> 2.18.0
>
>
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next prev parent reply other threads:[~2022-04-26 20:27 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 3:32 [PATCH 0/5] MediaTek MT8195 display binding Rex-BC Chen
2022-04-19 3:32 ` [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: add power and gce properties Rex-BC Chen
2022-04-19 14:54 ` Matthias Brugger
2022-04-26 18:31 ` Rob Herring
2022-04-27 2:47 ` Jason-JH Lin
2022-04-19 3:32 ` [PATCH 2/5] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding Rex-BC Chen
2022-04-19 14:57 ` Matthias Brugger
2022-04-19 3:32 ` [PATCH 3/5] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 Rex-BC Chen
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:54 ` Rex-BC Chen
2022-04-19 14:57 ` Matthias Brugger
2022-04-19 15:51 ` Chun-Kuang Hu
2022-04-20 3:15 ` Rex-BC Chen
2022-04-26 20:25 ` Rob Herring [this message]
2022-04-27 1:33 ` Nancy.Lin
2022-04-19 3:32 ` [PATCH 4/5] dt-bindings: reset: mt8195: add vdosys1 reset control bit Rex-BC Chen
2022-04-19 3:32 ` [PATCH 5/5] dt-bindings: mediatek: add ethdr definition for mt8195 Rex-BC Chen
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:55 ` Rex-BC Chen
2022-04-25 16:34 ` Rob Herring
2022-04-27 2:37 ` Nancy.Lin
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