From: Mark Brown <broonie@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, peterz@infradead.org,
acme@kernel.org, mark.rutland@arm.com, will@kernel.org,
catalin.marinas@arm.com, Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH V3 1/7] arm64/perf: Add BRBE registers and fields
Date: Thu, 29 Sep 2022 12:29:38 +0100 [thread overview]
Message-ID: <YzWBokiO1KSZNtcl@sirena.org.uk> (raw)
In-Reply-To: <20220929075857.158358-2-anshuman.khandual@arm.com>
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On Thu, Sep 29, 2022 at 01:28:51PM +0530, Anshuman Khandual wrote:
Thanks for doing this work - I did spot a few small issues though.
> /* id_aa64dfr0 */
> +#define ID_AA64DFR0_BRBE_SHIFT 52
> #define ID_AA64DFR0_MTPMU_SHIFT 48
> #define ID_AA64DFR0_TRBE_SHIFT 44
> #define ID_AA64DFR0_TRACE_FILT_SHIFT 40
> @@ -848,6 +952,9 @@
> #define ID_AA64DFR0_PMSVER_8_2 0x1
> #define ID_AA64DFR0_PMSVER_8_3 0x2
>
> +#define ID_AA64DFR0_BRBE 0x1
> +#define ID_AA64DFR0_BRBE_V1P1 0x2
> +
> #define ID_DFR0_PERFMON_SHIFT 24
>
> #define ID_DFR0_PERFMON_8_0 0x3
This is already done in -next as a result of ID_AA64DFR0_EL1 being
converted, the enumberation define comes out as
ID_AA64DFR0_EL1_BRBE_BRBE_V1P1.
> +# This is just a dummy register declaration to get all common field masks and
> +# shifts for accessing given BRBINF contents.
> +Sysreg BRBINF_EL1 2 1 8 0 0
> +Res0 63:47
> +Field 46 CCU
> +Field 45:32 CC
> +Res0 31:18
> +Field 17 LASTFAILED
> +Field 16 TX
According to DDI0487I.a bit 16 is called T not TX.
> +Res0 15:14
> +Enum 13:8 TYPE
It's probably worth noting in the comment the issue with Enums here
that's meaning you're not using a SysregFields - I'm not sure what
people will think of this but providing a definition using the ID for
the 0th register does seem expedient.
> +Enum 7:6 EL
> + 0b00 EL0
> + 0b01 EL1
> + 0b10 EL2
> +EndEnum
According to DDI0487I.a 0b11 has the value EL3 (when FEAT_BRBEv1p1).
> +Sysreg BRBCR_EL1 2 1 9 0 0
> +Res0 63:24
> +Field 23 EXCEPTION
> +Field 22 ERTN
> +Res0 21:9
> +Field 8 FZP
> +Field 7 ZERO
According to DDI0487I.a bit 7 is Res0.
> +Field 2 ZERO1
According to DDI0487I.a bit 2 is Res0.
> +Sysreg BRBFCR_EL1 2 1 9 0 1
> +Field 16 ENL
Accoding to DDI0487I.a this is EnI (ie, an L not an I).
> +Sysreg BRBINFINJ_EL1 2 1 9 1 0
> +Field 16 TX
According to DDI0487I.a this is T not TX.
> +Enum 7:6 EL
> + 0b00 EL0
> + 0b01 EL1
> + 0b10 EL2
> +EndEnum
According to DDI0487I.a 0b11 has the value EL3 (when FEAT_BRBEv1p1).
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next prev parent reply other threads:[~2022-09-29 11:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 7:58 [PATCH V3 0/7] arm64/perf: Enable branch stack sampling Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 1/7] arm64/perf: Add BRBE registers and fields Anshuman Khandual
2022-09-29 11:29 ` Mark Brown [this message]
2022-09-30 4:07 ` Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 2/7] arm64/perf: Update struct arm_pmu for BRBE Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 3/7] arm64/perf: Update struct pmu_hw_events " Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 4/7] driver/perf/arm_pmu_platform: Add support for BRBE attributes detection Anshuman Khandual
2022-10-06 13:37 ` James Clark
2022-10-10 14:17 ` James Clark
2022-10-11 9:21 ` Anshuman Khandual
2022-10-12 7:50 ` Anshuman Khandual
2022-10-11 9:16 ` Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 5/7] arm64/perf: Drive BRBE from perf event states Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 6/7] arm64/perf: Add BRBE driver Anshuman Khandual
2022-09-29 7:58 ` [PATCH V3 7/7] arm64/perf: Enable branch stack sampling Anshuman Khandual
2022-10-10 13:55 ` James Clark
2022-10-10 15:48 ` Suzuki K Poulose
2022-10-11 9:27 ` Anshuman Khandual
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