From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2FBC49EA6 for ; Thu, 24 Jun 2021 13:40:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EED55613F6 for ; Thu, 24 Jun 2021 13:40:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EED55613F6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:CC:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6PKz8w5oUxPBwc9t9IknqoeFn5m3+51I17zFwKtIJ70=; b=Dfuo2+5+KIUggbMvcQ7ELBqwX7 fS7VI4rophoKA7LC3f1zGfChjccHWUumLUWdGUbIBT2AwhQ3jo74xyb5WpJmyvpUY1kxHntEuAHY6 /aiIpLlRQQVxmNdyY092IPtrXzKmR/AtKmaPJDMt96zIjlj0dJfr2nI/6arxSSyss9KnIYH09c+dx eycwp9jkGr/zfCFfahSOTETZdJVf03yov1ifa4hiAkP5zoaaiBPdSa2U3ZELn3vz0vXbgltjk8lZF 9igQNHpTnK0efbclhWw402ygdtSW2PkkXs3NFRksB+q1W71abGvYag5TCci9yd8BrRN8zrEdP6WtM z3bl/pHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lwPZ8-00ErcN-Mc; Thu, 24 Jun 2021 13:38:47 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lwPZ4-00ErW3-36 for linux-arm-kernel@lists.infradead.org; Thu, 24 Jun 2021 13:38:44 +0000 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4G9h2t1mVRz739f; Thu, 24 Jun 2021 21:35:18 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Thu, 24 Jun 2021 21:38:34 +0800 Received: from [10.67.102.67] (10.67.102.67) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 24 Jun 2021 21:38:34 +0800 Subject: Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging To: Will Deacon CC: , , , , , , , , , , , References: <1624360271-17525-1-git-send-email-huangguangbin2@huawei.com> <1624360271-17525-2-git-send-email-huangguangbin2@huawei.com> <20210622121630.GC30757@willie-the-truck> From: "huangguangbin (A)" Message-ID: Date: Thu, 24 Jun 2021 21:38:34 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20210622121630.GC30757@willie-the-truck> X-Originating-IP: [10.67.102.67] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_063842_726359_E77A651C X-CRM114-Status: GOOD ( 23.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021/6/22 20:16, Will Deacon wrote: > On Tue, Jun 22, 2021 at 07:11:09PM +0800, Guangbin Huang wrote: >> From: Xiongfeng Wang >> >> DGH prohibits merging memory accesses with Normal-NC or Device-GRE >> attributes before the hint instruction with any memory accesses >> appearing after the hint instruction. Provide macros to expose it to the >> arch code. > > Hmm. > > The architecture states: > > | DGH is a hint instruction. A DGH instruction is not expected to be > | performance optimal to merge memory accesses with Normal Non-cacheable > | or Device-GRE attributes appearing in program order before the hint > | instruction with any memory accesses appearing after the hint instruction > | into a single memory transaction on an interconnect. > > which doesn't make a whole lot of sense to me, in all honesty. > Thanks for your review and modification of commit log. >> Signed-off-by: Xiongfeng Wang >> Signed-off-by: Cheng Jian >> Signed-off-by: Yufeng Mo >> --- >> arch/arm64/include/asm/assembler.h | 7 +++++++ >> arch/arm64/include/asm/barrier.h | 1 + >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h >> index 8418c1bd8f04..d723899328bd 100644 >> --- a/arch/arm64/include/asm/assembler.h >> +++ b/arch/arm64/include/asm/assembler.h >> @@ -90,6 +90,13 @@ >> .endm >> >> /* >> + * Data gathering hint >> + */ >> + .macro dgh >> + hint #6 >> + .endm >> + >> +/* >> * RAS Error Synchronization barrier >> */ >> .macro esb >> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h >> index 451e11e5fd23..02e1735706d2 100644 >> --- a/arch/arm64/include/asm/barrier.h >> +++ b/arch/arm64/include/asm/barrier.h >> @@ -22,6 +22,7 @@ >> #define dmb(opt) asm volatile("dmb " #opt : : : "memory") >> #define dsb(opt) asm volatile("dsb " #opt : : : "memory") >> >> +#define dgh() asm volatile("hint #6" : : : "memory") > > Although I'm fine with this in arm64, I don't think this is the interface > which drivers should be using. Instead, once we know what this instruction > is supposed to do, we should look at exposing it as part of the I/O barriers > and providing a NOP implementation for other architectures. That way, > drivers can use it without having to have the #ifdef CONFIG_ARM64 stuff that > you have in the later patches here. > > Will > . > Ok, thanks, we will try to implement a new I/O barriers interface as your opinion and repost a new version after we test ok. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel