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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id 123-20020a251381000000b00da0abddeb02sm296560ybt.34.2023.11.20.15.31.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Nov 2023 15:31:15 -0800 (PST) Message-ID: Date: Mon, 20 Nov 2023 15:31:12 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 15/19] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit Content-Language: en-US To: Peter Griffin Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org References: <20231120212037.911774-1-peter.griffin@linaro.org> <20231120212037.911774-16-peter.griffin@linaro.org> <5ee955e4-4c22-4696-8001-1e4f24952eeb@roeck-us.net> <0c37e32f-079c-4b91-a9db-1c1c2df299b1@roeck-us.net> From: Guenter Roeck Autocrypt: addr=linux@roeck-us.net; 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charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/20/23 15:20, Peter Griffin wrote: > Hi Guenter, > > On Mon, 20 Nov 2023 at 23:03, Guenter Roeck wrote: >> >> On 11/20/23 14:45, Peter Griffin wrote: >>> Hi Guenter, >>> >>> Thanks for the review. >>> >>> On Mon, 20 Nov 2023 at 22:00, Guenter Roeck wrote: >>>> >>>> On 11/20/23 13:20, Peter Griffin wrote: >>>>> The WDT uses the CPU core signal DBGACK to determine whether the SoC >>>>> is running in debug mode or not. If the DBGACK signal is asserted and >>>>> DBGACK_MASK is enabled, then WDT output and interrupt is masked. >>>>> >>>>> Presence of the DBGACK_MASK bit is determined by adding a new >>>>> QUIRK_HAS_DBGACK_BIT quirk. Currently only gs101 SoC is known to have >>>>> the DBGACK_MASK bit so add the quirk to drv_data_gs101_cl1 and >>>>> drv_data_gs101_cl1 quirks. >>>>> >>>>> Signed-off-by: Peter Griffin >>>>> --- >>>>> drivers/watchdog/s3c2410_wdt.c | 32 +++++++++++++++++++++++++++----- >>>>> 1 file changed, 27 insertions(+), 5 deletions(-) >>>>> >>>>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c >>>>> index 08b8c57dd812..ed561deeeed9 100644 >>>>> --- a/drivers/watchdog/s3c2410_wdt.c >>>>> +++ b/drivers/watchdog/s3c2410_wdt.c >>>>> @@ -34,9 +34,10 @@ >>>>> >>>>> #define S3C2410_WTCNT_MAXCNT 0xffff >>>>> >>>>> -#define S3C2410_WTCON_RSTEN (1 << 0) >>>>> -#define S3C2410_WTCON_INTEN (1 << 2) >>>>> -#define S3C2410_WTCON_ENABLE (1 << 5) >>>>> +#define S3C2410_WTCON_RSTEN (1 << 0) >>>>> +#define S3C2410_WTCON_INTEN (1 << 2) >>>>> +#define S3C2410_WTCON_ENABLE (1 << 5) >>>>> +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) >>>>> >>>>> #define S3C2410_WTCON_DIV16 (0 << 3) >>>>> #define S3C2410_WTCON_DIV32 (1 << 3) >>>>> @@ -107,12 +108,16 @@ >>>>> * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) >>>>> * with "watchdog counter enable" bit. That bit should be set to make watchdog >>>>> * counter running. >>>>> + * >>>>> + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Enables masking >>>>> + * WDT interrupt and reset request according to CPU core DBGACK signal. >>>> >>>> This is a bit difficult to understand. I _think_ it means that the DBGACK_MASK bit >>>> has to be set to be able to trigger interrupt and reset requests. >>> >>> Not quite, it is a bit that controls masking the watchdog outputs when the SoC >>> is in debug mode. >>> >>>> "masking" normally refers to disabling something (at least in interrupt context). >>>> "Enables masking WDT interrupt" sounds like the bit has to be set in order to >>>> be able to disable interupts, and the code below suggests that the bit has to be >>>> set for the driver to work. Is that the case ? It might make sense to explain this >>>> a bit further. >>> >>> Maybe I explained it more clearly in the commit message than the comment >>> >>> "The WDT uses the CPU core signal DBGACK to determine whether the SoC >>> is running in debug mode or not. If the DBGACK signal is asserted and >>> DBGACK_MASK is enabled, then WDT output and interrupt is masked." >>> >>> Is that any clearer? Or maybe simpler again >>> >>> "Enabling DBGACK_MASK bit masks the watchdog outputs when the SoC is >>> in debug mode. Debug mode is determined by the DBGACK CPU signal." >>> >>> Let me know what you think is the clearest and most succinct and I can >>> update the comment. >>> >> >> You are still using the term "masked" which I think just hides what >> the code is really doing. Why not just say "disable" ? > > The reason for using the "masked" terminology was that is what the > Watchdog IP TRM uses throughout to describe the feature. But I agree > just saying disable is clearer. > At least please say something like "masked (disabled)" if you want to use the term. Thanks, Guenter _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel