From: Jon Hunter <jonathanh@nvidia.com>
To: Joseph Lo <josephl@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: devicetree@vger.kernel.org,
Daniel Lezcano <daniel.lezcano@linaro.org>,
linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/6] dt-bindings: timer: add Tegra210 timer
Date: Thu, 24 Jan 2019 10:30:42 +0000 [thread overview]
Message-ID: <a5fec080-d388-5362-7f44-b50f7d7e1adf@nvidia.com> (raw)
In-Reply-To: <20190107032810.13522-2-josephl@nvidia.com>
On 07/01/2019 03:28, Joseph Lo wrote:
> The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
> timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
> from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
> (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
> or watchdog interrupts.
>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-kernel@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> .../bindings/timer/nvidia,tegra210-timer.txt | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
> new file mode 100644
> index 000000000000..ba511220a669
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
> @@ -0,0 +1,25 @@
> +NVIDIA Tegra210 timer
> +
> +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
> +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
> +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
> +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
> +or watchdog interrupts.
> +
> +Required properties:
> +- compatible : "nvidia,tegra210-timer".
> +- reg : Specifies base physical address and size of the registers.
> +- interrupts : A list of 4 interrupts; one per each of TMR10 through TMR13.
Why do we only add the interrupts for TMR10 - TMR13? What about the others?
Cheers
Jon
--
nvpublic
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next prev parent reply other threads:[~2019-01-24 10:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-07 3:28 [PATCH 0/6] Add CPUidle support for Tegra210 Joseph Lo
2019-01-07 3:28 ` [PATCH 1/6] dt-bindings: timer: add Tegra210 timer Joseph Lo
2019-01-11 22:21 ` Rob Herring
2019-01-24 10:30 ` Jon Hunter [this message]
2019-01-25 3:23 ` Joseph Lo
2019-01-25 12:01 ` Jon Hunter
2019-01-25 12:06 ` Jon Hunter
2019-01-28 3:09 ` Joseph Lo
2019-01-07 3:28 ` [PATCH 2/6] clocksource: tegra: add Tegra210 timer driver Joseph Lo
2019-01-24 11:09 ` Jon Hunter
2019-01-25 4:12 ` Joseph Lo
2019-01-07 3:28 ` [PATCH 3/6] arm64: dts: tegra210: fix timer node Joseph Lo
2019-01-24 11:16 ` Jon Hunter
2019-01-25 3:56 ` Joseph Lo
2019-01-07 3:28 ` [PATCH 4/6] arm64: dts: tegra210: add CPU idle states properties Joseph Lo
2019-01-24 11:21 ` Jon Hunter
2019-01-25 3:58 ` Joseph Lo
2019-01-07 3:28 ` [PATCH 5/6] arm64: dts: tegra210-p2180: Enable CPU idle support Joseph Lo
2019-01-07 3:28 ` [PATCH 6/6] arm64: dts: tegra210-smaug: " Joseph Lo
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