From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88B9EC2BBC7 for ; Mon, 13 Apr 2020 03:35:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52BB5206C3 for ; Mon, 13 Apr 2020 03:35:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OP+62D/t" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52BB5206C3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vU2DiHDBbYYK+z61/Ms5mDQiCSoxR41MQ52Wa6YchU0=; b=OP+62D/tmTLHos xIQdtsX5Fn1Cu+9IZr1h03wcgGxMSrvOvf4B4RHDBcW9ggkr0PHyvoNJrakHW+eItCGsgpD1n2stm pmV9Qb/5qzVgGN94UgfZAkHgcLufdELf5xWT3+nYBzgvDeDzzTtIcn/dOAwAlowZ6H0tN4AhZ9xxu kaK5AP8VuopaFDc+ze8XpcUtn4z8LZn2WgFvjIloMgoPXwOFiV+LRTemG+GYtcYVFqlCc5dEaNqiW 2buApoGe7C6O33Ib0kxP6EL5XMm2XoW8SSx1aDu3RXGZLuamDdGSzLWygk3ZDV52cHGYIiIAifOpt HCLiXCKf3B47pGSeRthQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jNpsr-0002s1-0O; Mon, 13 Apr 2020 03:35:41 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jNpso-0002rZ-5O for linux-arm-kernel@lists.infradead.org; Mon, 13 Apr 2020 03:35:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4227230E; Sun, 12 Apr 2020 20:35:37 -0700 (PDT) Received: from [10.163.1.49] (unknown [10.163.1.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 811A43F6C4; Sun, 12 Apr 2020 20:35:35 -0700 (PDT) Subject: Re: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register To: Will Deacon References: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com> <1580215149-21492-3-git-send-email-anshuman.khandual@arm.com> <20200409125526.GC13078@willie-the-truck> From: Anshuman Khandual Message-ID: Date: Mon, 13 Apr 2020 09:05:28 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20200409125526.GC13078@willie-the-truck> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200412_203538_248713_54B40341 X-CRM114-Status: GOOD ( 14.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04/09/2020 06:25 PM, Will Deacon wrote: > On Tue, Jan 28, 2020 at 06:09:05PM +0530, Anshuman Khandual wrote: >> Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a >> specification. Except RAS and AMU, all other feature bits are now enabled. >> >> Cc: Catalin Marinas >> Cc: Will Deacon >> Cc: Suzuki K Poulose >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >> arch/arm64/include/asm/sysreg.h | 3 +++ >> arch/arm64/kernel/cpufeature.c | 2 ++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 054aab7ebf1b..469d61c8fabf 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -718,6 +718,9 @@ >> #define ID_ISAR6_DP_SHIFT 4 >> #define ID_ISAR6_JSCVT_SHIFT 0 >> >> +#define ID_PFR0_DIT_SHIFT 24 >> +#define ID_PFR0_CSV2_SHIFT 16 >> + >> #define ID_PFR2_SSBS_SHIFT 4 >> #define ID_PFR2_CSV3_SHIFT 0 >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index c1e837fc8f97..9e4dab15c608 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = { >> }; >> >> static const struct arm64_ftr_bits ftr_id_pfr0[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), > > Same comment as CSV3 here. Why is CSV2 being treated as strict here, but not > in the aa64* register? Sure, will change. > > Will > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel