[PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[Suman Anna]

Hi Tero,

The following series adds the DT nodes for the MCU SRAM present within
the MCU domain for both AM65x and J721E SoCs. The first 2 patches enable
the MCU SRAM node to be probed properly on AM65x SoCs, and the third
patch the equivalent for J721E SoCs. The third patch depends on the
base J721E support patch series from Nishanth [1].

The last patch is not related to MCU SRAM, but adds the ranges for the
R5F cluster that is also present in the MCU domain in preparation for
the R5F nodes.

regards
Suman

[1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=121189 

Suman Anna (4):
  arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
  arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
  arm64: dts: ti: k3-j721e: Add the MCU SRAM node
  arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes

 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am65.dtsi             | 6 ++++++
 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
 3 files changed, 22 insertions(+)

-- 
2.21.0


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[PATCH 1/4] arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes

[Suman Anna]

Add the address space for the MCU SRAM memory to the ranges property
of the cbass_mcu interconnect node so that the addresses within the
mcu_sram nodes and its children can be translated properly by the
relevant OF address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index 68b3f954f1d1..abb085f5e784 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -72,6 +72,7 @@
 			 /* MCUSS Range */
 			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
 			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
 			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
 			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
 			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
@@ -83,6 +84,7 @@
 			#size-cells = <2>;
 			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
 				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
 				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
 				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
 				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
-- 
2.21.0


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[PATCH 2/4] arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node

[Suman Anna]

Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
The K3 AM65x SoCs have 512 KB of such memory. Any specific memory range
within this RAM needed by a software module ought to be reserved using
an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 6f7d2b316ded..afc29eaa2638 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -17,6 +17,14 @@
 			power-domains = <&k3_pds 149>;
 	};
 
+	mcu_ram: sram@41c00000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x41c00000 0x00 0x80000>;
+		ranges = <0x0 0x00 0x41c00000 0x80000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
 	mcu_i2c0: i2c@40b00000 {
 		compatible = "ti,am654-i2c", "ti,omap4-i2c";
 		reg = <0x0 0x40b00000 0x0 0x100>;
-- 
2.21.0


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[PATCH 3/4] arm64: dts: ti: k3-j721e: Add the MCU SRAM node

[Suman Anna]

Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
The K3 J721E SoCs have 1 MB of such memory. Any specific memory range
within this RAM needed by a driver/software module ought to be reserved
using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index b72e033fa159..397ef715e145 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -44,6 +44,14 @@
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	mcu_ram: sram@41c00000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x41c00000 0x00 0x100000>;
+		ranges = <0x0 0x00 0x41c00000 0x100000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
 	wkup_uart0: serial@42300000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x42300000 0x00 0x100>;
-- 
2.21.0


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[PATCH 4/4] arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes

[Suman Anna]

Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index abb085f5e784..f71c8f50a5e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -72,6 +72,8 @@
 			 /* MCUSS Range */
 			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
 			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
 			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
 			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
 			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
@@ -84,6 +86,8 @@
 			#size-cells = <2>;
 			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
 				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
 				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
 				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
 				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
-- 
2.21.0


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Re: [PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[Andrew F. Davis]

On 6/5/19 12:34 PM, Suman Anna wrote:
> Hi Tero,
> 
> The following series adds the DT nodes for the MCU SRAM present within
> the MCU domain for both AM65x and J721E SoCs. The first 2 patches enable
> the MCU SRAM node to be probed properly on AM65x SoCs, and the third
> patch the equivalent for J721E SoCs. The third patch depends on the
> base J721E support patch series from Nishanth [1].
> 
> The last patch is not related to MCU SRAM, but adds the ranges for the
> R5F cluster that is also present in the MCU domain in preparation for
> the R5F nodes.
> 

Why not have this last patch as part of the series adding the R5F nodes?

Andrew

> regards
> Suman
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=121189
> 
> Suman Anna (4):
>    arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
>    arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
>    arm64: dts: ti: k3-j721e: Add the MCU SRAM node
>    arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
> 
>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 8 ++++++++
>   arch/arm64/boot/dts/ti/k3-am65.dtsi             | 6 ++++++
>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
>   3 files changed, 22 insertions(+)
> 

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Re: [PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[Suman Anna]

On 6/5/19 11:53 AM, Andrew F. Davis wrote:
> On 6/5/19 12:34 PM, Suman Anna wrote:
>> Hi Tero,
>>
>> The following series adds the DT nodes for the MCU SRAM present within
>> the MCU domain for both AM65x and J721E SoCs. The first 2 patches enable
>> the MCU SRAM node to be probed properly on AM65x SoCs, and the third
>> patch the equivalent for J721E SoCs. The third patch depends on the
>> base J721E support patch series from Nishanth [1].
>>
>> The last patch is not related to MCU SRAM, but adds the ranges for the
>> R5F cluster that is also present in the MCU domain in preparation for
>> the R5F nodes.
>>
> 
> Why not have this last patch as part of the series adding the R5F nodes?

The patch can be applied independently as is, no reason to wait until I
post those.

regards
Suman

> 
> Andrew
> 
>> regards
>> Suman
>>
>> [1]
>> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=121189
>>
>> Suman Anna (4):
>>    arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
>>    arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
>>    arm64: dts: ti: k3-j721e: Add the MCU SRAM node
>>    arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
>>
>>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 8 ++++++++
>>   arch/arm64/boot/dts/ti/k3-am65.dtsi             | 6 ++++++
>>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
>>   3 files changed, 22 insertions(+)
>>


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Re: [PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[Andrew F. Davis]

On 6/5/19 1:01 PM, Suman Anna wrote:
> On 6/5/19 11:53 AM, Andrew F. Davis wrote:
>> On 6/5/19 12:34 PM, Suman Anna wrote:
>>> Hi Tero,
>>>
>>> The following series adds the DT nodes for the MCU SRAM present within
>>> the MCU domain for both AM65x and J721E SoCs. The first 2 patches enable
>>> the MCU SRAM node to be probed properly on AM65x SoCs, and the third
>>> patch the equivalent for J721E SoCs. The third patch depends on the
>>> base J721E support patch series from Nishanth [1].
>>>
>>> The last patch is not related to MCU SRAM, but adds the ranges for the
>>> R5F cluster that is also present in the MCU domain in preparation for
>>> the R5F nodes.
>>>
>>
>> Why not have this last patch as part of the series adding the R5F nodes?
> 
> The patch can be applied independently as is, no reason to wait until I
> post those.
> 

No reason not to wait either.. plus it would keep related changes in the 
same series.

Anyway, I don't have any problem with this, was just asking as I was not 
sure if I was missing some hidden dependency between the nodes.

Andrew

> regards
> Suman
> 
>>
>> Andrew
>>
>>> regards
>>> Suman
>>>
>>> [1]
>>> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=121189
>>>
>>> Suman Anna (4):
>>>     arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
>>>     arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
>>>     arm64: dts: ti: k3-j721e: Add the MCU SRAM node
>>>     arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
>>>
>>>    arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 8 ++++++++
>>>    arch/arm64/boot/dts/ti/k3-am65.dtsi             | 6 ++++++
>>>    arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
>>>    3 files changed, 22 insertions(+)
>>>
> 

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Re: [PATCH 0/4] Add MCU SRAM nodes for TI K3 SoCs

[Tero Kristo]

On 05/06/2019 19:34, Suman Anna wrote:
> Hi Tero,
> 
> The following series adds the DT nodes for the MCU SRAM present within
> the MCU domain for both AM65x and J721E SoCs. The first 2 patches enable
> the MCU SRAM node to be probed properly on AM65x SoCs, and the third
> patch the equivalent for J721E SoCs. The third patch depends on the
> base J721E support patch series from Nishanth [1].
> 
> The last patch is not related to MCU SRAM, but adds the ranges for the
> R5F cluster that is also present in the MCU domain in preparation for
> the R5F nodes.
> 
> regards
> Suman
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=121189

Queuing patches 1,2 and 4 towards 5.3 thanks.

Patch #3 is waiting until I can sort out j7 dependencies, which should 
happen later this week.

-Tero

> 
> Suman Anna (4):
>    arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
>    arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
>    arm64: dts: ti: k3-j721e: Add the MCU SRAM node
>    arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
> 
>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 8 ++++++++
>   arch/arm64/boot/dts/ti/k3-am65.dtsi             | 6 ++++++
>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
>   3 files changed, 22 insertions(+)
> 

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Re: [PATCH 3/4] arm64: dts: ti: k3-j721e: Add the MCU SRAM node

[Tero Kristo]

On 05/06/2019 19:34, Suman Anna wrote:
> Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
> The K3 J721E SoCs have 1 MB of such memory. Any specific memory range
> within this RAM needed by a driver/software module ought to be reserved
> using an appropriate child node.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>

Queuing for 5.3, thanks.

-Tero

> ---
>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index b72e033fa159..397ef715e145 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -44,6 +44,14 @@
>   		pinctrl-single,function-mask = <0xffffffff>;
>   	};
>   
> +	mcu_ram: sram@41c00000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00 0x41c00000 0x00 0x100000>;
> +		ranges = <0x0 0x00 0x41c00000 0x100000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +	};
> +
>   	wkup_uart0: serial@42300000 {
>   		compatible = "ti,j721e-uart", "ti,am654-uart";
>   		reg = <0x00 0x42300000 0x00 0x100>;
> 

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