From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A5C0C433EF for ; Mon, 29 Nov 2021 14:56:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=po/F9WTu0w01BbwA43/CVKIv80KU8bUu370Y2dzLvyA=; b=OBSWTk7m5fC5Jt ooC4e5DQqmGZXp+Qw9QtWRJoXFIt6rtXhCFh1QmxLu24gNrSuESKBAC84Qqm/6jVPkVgBeAub6UZf UEywefALVFhkv3+3kjkWahbA147lmuhX74ZOijIzb2JMuFeE9aBqwn3U72TZkBLqHxDcHvJJ3N2+k RrjTGeAp7yQlCy2jWyP80l4EnXJ9FT/mAgitoW35GYsNZp2tDjZVNvSJKW3DaJ3xhRuM7ZIRJicoJ tqhjl5Luhut/nbMEjjOMqncup9FFPMvOVFYNktLqJPOggSmdPVt+kpYyNvn55ytTVv6FLHjxzwPM/ FCfy3N6/C+LgUL2fh6mA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mri35-001Bia-0D; Mon, 29 Nov 2021 14:54:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mri31-001BhT-Ct for linux-arm-kernel@lists.infradead.org; Mon, 29 Nov 2021 14:54:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F18AD1042; Mon, 29 Nov 2021 06:54:25 -0800 (PST) Received: from [10.57.34.182] (unknown [10.57.34.182]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7D1C3F766; Mon, 29 Nov 2021 06:54:21 -0800 (PST) Message-ID: Date: Mon, 29 Nov 2021 14:54:18 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [patch 33/37] iommu/arm-smmu-v3: Use msi_get_virq() Content-Language: en-GB To: Thomas Gleixner , Will Deacon Cc: Nishanth Menon , Mark Rutland , Stuart Yoder , linux-pci@vger.kernel.org, Ashok Raj , Marc Zygnier , x86@kernel.org, Sinan Kaya , iommu@lists.linux-foundation.org, Bjorn Helgaas , Megha Dey , Jason Gunthorpe , Kevin Tian , Alex Williamson , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Tero Kristo , Greg Kroah-Hartman , LKML , Vinod Koul , dmaengine@vger.kernel.org References: <20211126224100.303046749@linutronix.de> <20211126230525.885757679@linutronix.de> <20211129105506.GA22761@willie-the-truck> <76a1b5c1-01c8-bb30-6105-b4073dc23065@arm.com> <87czmjdnw9.ffs@tglx> From: Robin Murphy In-Reply-To: <87czmjdnw9.ffs@tglx> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_065427_524774_06766424 X-CRM114-Status: GOOD ( 16.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-11-29 14:42, Thomas Gleixner wrote: > On Mon, Nov 29 2021 at 13:13, Robin Murphy wrote: >> On 2021-11-29 10:55, Will Deacon wrote: >>>> - } >>>> + smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); >>>> + smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); >>>> + smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); >>> >>> Prviously, if retrieval of the MSI failed then we'd fall back to wired >>> interrupts. Now, I think we'll clobber the interrupt with 0 instead. Can >>> we make the assignments to smmu->*irq here conditional on the MSI being >>> valid, please? >> >> I was just looking at that too, but reached the conclusion that it's >> probably OK, since consumption of this value later is gated on >> ARM_SMMU_FEAT_PRI, so the fact that it changes from 0 to an error value >> in the absence of PRI should make no practical difference. > > It's actually 0 when the vector cannot be found. Oh, -1 for my reading comprehension but +1 for my confidence in the patch then :) I'll let Will have the final say over how cautious we really want to be here, but as far as I'm concerned it's a welcome cleanup as-is. Ditto for patch #32 based on the same reasoning, although I don't have a suitable test platform on-hand to sanity-check that one. Cheers, Robin. >> If we don't have MSIs at all, we'd presumably still fail earlier >> either at the dev->msi_domain check or upon trying to allocate the >> vectors, so we'll still fall back to any previously-set wired values >> before getting here. The only remaining case is if we've >> *successfully* allocated the expected number of vectors yet are then >> somehow unable to retrieve one or more of them - presumably the system >> has to be massively borked for that to happen, at which point do we >> really want to bother trying to reason about anything? > > Probably not. At that point something is going to explode sooner than > later in colorful ways. > > Thanks, > > tglx > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel