Re: [PATCH v6 2/2] remoteproc: mediatek: Support mt8186 scp

[allen-kh.cheng <allen-kh.cheng@mediatek.com>]

On Tue, 2022-03-15 at 09:13 -0600, Mathieu Poirier wrote:
> On Tue, Mar 15, 2022 at 08:47:47PM +0800, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > 
> > Add SCP support for mt8186
> 
> V5 of this patchset is already in rproc-next and as such this one
> does not
> apply.
> 
> > 
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> 
> As far as I can see from the mailing list interactions, Angelo did
> not review
> the new section about cache initialisation and yet his RoB is
> present.  And to
> make matters worse he was not on the recipient list, which I have
> corrected.
> 
> Thanks,
> Mathieu
> 
Hi Mathieu,

Thanks for your friendly reminder.

I'll pay more attention to that next time.

Thanks,
Allen

> > ---
> >  drivers/remoteproc/mtk_common.h |  3 +++
> >  drivers/remoteproc/mtk_scp.c    | 42
> > +++++++++++++++++++++++++++++++++
> >  2 files changed, 45 insertions(+)
> > 
> > diff --git a/drivers/remoteproc/mtk_common.h
> > b/drivers/remoteproc/mtk_common.h
> > index 5ff3867c72f3..71ce4977cb0b 100644
> > --- a/drivers/remoteproc/mtk_common.h
> > +++ b/drivers/remoteproc/mtk_common.h
> > @@ -32,6 +32,9 @@
> >  #define MT8183_SCP_CACHESIZE_8KB	BIT(8)
> >  #define MT8183_SCP_CACHE_CON_WAYEN	BIT(10)
> >  
> > +#define MT8186_SCP_L1_SRAM_PD_P1	0x40B0
> > +#define MT8186_SCP_L1_SRAM_PD_p2	0x40B4
> > +
> >  #define MT8192_L2TCM_SRAM_PD_0		0x10C0
> >  #define MT8192_L2TCM_SRAM_PD_1		0x10C4
> >  #define MT8192_L2TCM_SRAM_PD_2		0x10C8
> > diff --git a/drivers/remoteproc/mtk_scp.c
> > b/drivers/remoteproc/mtk_scp.c
> > index dcddb33e9997..11be6b4235eb 100644
> > --- a/drivers/remoteproc/mtk_scp.c
> > +++ b/drivers/remoteproc/mtk_scp.c
> > @@ -383,6 +383,35 @@ static void mt8192_power_off_sram(void __iomem
> > *addr)
> >  		writel(GENMASK(i, 0), addr);
> >  }
> >  
> > +static int mt8186_scp_before_load(struct mtk_scp *scp)
> > +{
> > +	/* Clear SCP to host interrupt */
> > +	writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base +
> > MT8183_SCP_TO_HOST);
> > +
> > +	/* Reset clocks before loading FW */
> > +	writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
> > +	writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
> > +
> > +	/* Turn on the power of SCP's SRAM before using it. Enable 1
> > block per time*/
> > +	mt8192_power_on_sram(scp->reg_base + MT8183_SCP_SRAM_PDN);
> > +
> > +	/* Initialize TCM before loading FW. */
> > +	writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
> > +	writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
> > +	writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
> > +	writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
> > +
> > +	/*
> > +	 * Set I-cache and D-cache size before loading SCP FW.
> > +	 * SCP SRAM logical address may change when cache size setting
> > differs.
> > +	 */
> > +	writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
> > +	       scp->reg_base + MT8183_SCP_CACHE_CON);
> > +	writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base +
> > MT8183_SCP_DCACHE_CON);
> > +
> > +	return 0;
> > +}
> > +
> >  static int mt8192_scp_before_load(struct mtk_scp *scp)
> >  {
> >  	/* clear SPM interrupt, SCP2SPM_IPC_CLR */
> > @@ -874,6 +903,18 @@ static const struct mtk_scp_of_data
> > mt8183_of_data = {
> >  	.ipi_buf_offset = 0x7bdb0,
> >  };
> >  
> > +static const struct mtk_scp_of_data mt8186_of_data = {
> > +	.scp_clk_get = mt8195_scp_clk_get,
> > +	.scp_before_load = mt8186_scp_before_load,
> > +	.scp_irq_handler = mt8183_scp_irq_handler,
> > +	.scp_reset_assert = mt8183_scp_reset_assert,
> > +	.scp_reset_deassert = mt8183_scp_reset_deassert,
> > +	.scp_stop = mt8183_scp_stop,
> > +	.scp_da_to_va = mt8183_scp_da_to_va,
> > +	.host_to_scp_reg = MT8183_HOST_TO_SCP,
> > +	.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,
> > +};
> > +
> >  static const struct mtk_scp_of_data mt8192_of_data = {
> >  	.scp_clk_get = mt8192_scp_clk_get,
> >  	.scp_before_load = mt8192_scp_before_load,
> > @@ -900,6 +941,7 @@ static const struct mtk_scp_of_data
> > mt8195_of_data = {
> >  
> >  static const struct of_device_id mtk_scp_of_match[] = {
> >  	{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data
> > },
> > +	{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data
> > },
> >  	{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data
> > },
> >  	{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data
> > },
> >  	{},
> > -- 
> > 2.18.0
> > 


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel