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Sat, 28 May 2022 11:37:00 +0100 MIME-Version: 1.0 Date: Sat, 28 May 2022 11:37:00 +0100 From: Marc Zyngier To: Anand Gore Cc: Linux ARM List , dan.beygelman@broadcom.com, samyon.furman@broadcom.com, florian.fainelli@broadcom.com, William Zhang , tomer.yacoby@broadcom.com, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, Broadcom internal kernel review list , Florian Fainelli , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] ARM64: dts: add dts files for bcmbca SoC bcm6858 In-Reply-To: <20220527101336.1.I66ae43da75911b704f02a759f70d66bc7e542885@changeid> References: <20220527171356.2461297-1-anand.gore@broadcom.com> <20220527101336.1.I66ae43da75911b704f02a759f70d66bc7e542885@changeid> User-Agent: Roundcube Webmail/1.4.13 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: anand.gore@broadcom.com, linux-arm-kernel@lists.infradead.org, dan.beygelman@broadcom.com, samyon.furman@broadcom.com, florian.fainelli@broadcom.com, william.zhang@broadcom.com, tomer.yacoby@broadcom.com, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, bcm-kernel-feedback-list@broadcom.com, f.fainelli@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220528_033710_868247_4DEC1F52 X-CRM114-Status: GOOD ( 20.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-05-27 18:13, Anand Gore wrote: > Add dts for ARMv8 based broadband SoC BCM6858. > bcm6858.dtsi is the SoC description dts header > and bcm96858.dts is a simple dts file for Broadcom > BCM96858 Reference board that only enables the UART port. > > Signed-off-by: Anand Gore > > --- > > arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- > .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 120 ++++++++++++++++++ > .../boot/dts/broadcom/bcmbca/bcm96858.dts | 30 +++++ > 3 files changed, 152 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi > create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts > > diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile > b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile > index d5f89245336c..7d98b0787b8c 100644 > --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile > +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > -dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb > +dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb \ > + bcm96858.dtb > diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi > b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi > new file mode 100644 > index 000000000000..664b8f399d69 > --- /dev/null > +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi > @@ -0,0 +1,120 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2022 Broadcom Ltd. > + */ > + > +#include > +#include > + > +/ { > + compatible = "brcm,bcm6858", "brcm,bcmbca"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + B53_0: cpu@0 { > + compatible = "brcm,brahma-b53"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + > + B53_1: cpu@1 { > + compatible = "brcm,brahma-b53"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + > + B53_2: cpu@2 { > + compatible = "brcm,brahma-b53"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + > + B53_3: cpu@3 { > + compatible = "brcm,brahma-b53"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + L2_0: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = IRQ_TYPE_LEVEL_LOW)>, > + , > + , > + ; > + }; > + > + pmu: pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&B53_0>, <&B53_1>, > + <&B53_2>, <&B53_3>; > + }; > + > + clocks: clocks { > + periph_clk:periph-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + cpu_off = <1>; > + cpu_on = <2>; No. Either this is PSCI 0.2 (and inventing your own function numbers is pointless), or this isn't. Either way, this is wrong. > + }; > + > + axi@81000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0x81000000 0x0 0x4000>; > + > + gic: interrupt-controller@1000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0x1000 0x0 0x1000>, > + <0x0 0x2000 0x0 0x2000>; GIC400 has another two regions for GICH and GICV, and a maintenance interrupt. Please add both. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel