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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hieFz-0001oj-Pf; Wed, 03 Jul 2019 12:21:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hieFw-0001o8-B4 for linux-arm-kernel@lists.infradead.org; Wed, 03 Jul 2019 12:21:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A05A92B; Wed, 3 Jul 2019 05:20:58 -0700 (PDT) Received: from [10.1.197.61] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 646A03F703; Wed, 3 Jul 2019 05:20:57 -0700 (PDT) Subject: Re: [PATCH 07/59] KVM: arm64: nv: Add EL2 system registers to vcpu context To: Dave Martin References: <20190621093843.220980-1-marc.zyngier@arm.com> <20190621093843.220980-8-marc.zyngier@arm.com> <20190624125416.GQ2790@e103592.cambridge.arm.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <20190624125416.GQ2790@e103592.cambridge.arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190703_052100_473982_44BE4BDE X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Julien Thierry , Andre Przywara , Suzuki K Poulose , Christoffer Dall , Jintack Lim , James Morse , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/06/2019 13:54, Dave Martin wrote: > On Fri, Jun 21, 2019 at 10:37:51AM +0100, Marc Zyngier wrote: >> From: Jintack Lim >> >> ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When >> this bit is set, accessing EL2 registers in EL1 traps to EL2. In >> addition, executing the following instructions in EL1 will trap to EL2: >> tlbi, at, eret, and msr/mrs instructions to access SP_EL1. Most of the >> instructions that trap to EL2 with the NV bit were undef at EL1 prior to >> ARM v8.3. The only instruction that was not undef is eret. >> >> This patch sets up a handler for EL2 registers and SP_EL1 register >> accesses at EL1. The host hypervisor keeps those register values in >> memory, and will emulate their behavior. >> >> This patch doesn't set the NV bit yet. It will be set in a later patch >> once nested virtualization support is completed. >> >> Signed-off-by: Jintack Lim >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/kvm_host.h | 37 +++++++++++++++- >> arch/arm64/include/asm/sysreg.h | 50 ++++++++++++++++++++- >> arch/arm64/kvm/sys_regs.c | 74 ++++++++++++++++++++++++++++--- >> 3 files changed, 154 insertions(+), 7 deletions(-) >> >> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h >> index 4bcd9c1291d5..2d4290d2513a 100644 >> --- a/arch/arm64/include/asm/kvm_host.h >> +++ b/arch/arm64/include/asm/kvm_host.h >> @@ -173,12 +173,47 @@ enum vcpu_sysreg { >> APGAKEYLO_EL1, >> APGAKEYHI_EL1, >> >> - /* 32bit specific registers. Keep them at the end of the range */ >> + /* 32bit specific registers. */ > > Out of interest, why did we originally want these to be at the end? > Because they're not at the end any more... I seem to remember the original assembly switch code used that property. This is a long gone requirement, thankfully. > >> DACR32_EL2, /* Domain Access Control Register */ >> IFSR32_EL2, /* Instruction Fault Status Register */ >> FPEXC32_EL2, /* Floating-Point Exception Control Register */ >> DBGVCR32_EL2, /* Debug Vector Catch Register */ >> >> + /* EL2 registers sorted ascending by Op0, Op1, CRn, CRm, Op2 */ >> + FIRST_EL2_SYSREG, >> + VPIDR_EL2 = FIRST_EL2_SYSREG, >> + /* Virtualization Processor ID Register */ >> + VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ >> + SCTLR_EL2, /* System Control Register (EL2) */ >> + ACTLR_EL2, /* Auxiliary Control Register (EL2) */ >> + HCR_EL2, /* Hypervisor Configuration Register */ >> + MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ >> + CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ >> + HSTR_EL2, /* Hypervisor System Trap Register */ >> + HACR_EL2, /* Hypervisor Auxiliary Control Register */ >> + TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ >> + TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ >> + TCR_EL2, /* Translation Control Register (EL2) */ >> + VTTBR_EL2, /* Virtualization Translation Table Base Register */ >> + VTCR_EL2, /* Virtualization Translation Control Register */ >> + SPSR_EL2, /* EL2 saved program status register */ >> + ELR_EL2, /* EL2 exception link register */ >> + AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ >> + AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ >> + ESR_EL2, /* Exception Syndrome Register (EL2) */ >> + FAR_EL2, /* Hypervisor IPA Fault Address Register */ >> + HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ >> + MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ >> + AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ >> + VBAR_EL2, /* Vector Base Address Register (EL2) */ >> + RVBAR_EL2, /* Reset Vector Base Address Register */ >> + RMR_EL2, /* Reset Management Register */ >> + CONTEXTIDR_EL2, /* Context ID Register (EL2) */ >> + TPIDR_EL2, /* EL2 Software Thread ID Register */ >> + CNTVOFF_EL2, /* Counter-timer Virtual Offset register */ >> + CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ >> + SP_EL2, /* EL2 Stack Pointer */ >> + > > I wonder whether we could make these conditionally present somehow. Not > worth worrying about for now to save 200-odd bytes per vcpu though. With 8.4-NV, these 200 bytes turn into a whole 8kB (4kB page, plus almost 4kB of padding that I need to reduce one way or another). So I'm not too worried about this for now. I really want the NV code to always be present though, in order to avoid configuration related regressions. I'm not sure how to make this better. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel