From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73FA0C433EF for ; Fri, 29 Apr 2022 04:18:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:CC:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=9uELSIDntYoZZyT1H+9UyYUKWO1F7pzOT4zwbQNrLbw=; b=Xu/tGkynb3lQ81PTzvEP6oOQZk EUuQaBLINWDCKuu0EfrwM+pnn5uWr72gYGeR24ewykBW7r+Re8ZH9AMCFs+QGMAS4DTMuVEjSx8XO BAiUY4q2SUrGnH37f7s1juaepUjEZVaOYZGXZoPunXAUCDb/zaeiRA1IKIpesMm/BS4EWS3SgreWn foSG7Xl6qIB+5jGqaB441MERcjJOfcFNfEQoL3Zwha+KscesSzTuJFNnhkRXsYZ7bQniI+rHQuG3g BQZ0azuCbXjQ24hdhtzs9FS39R37TcrWAk4EQ55VbWY8cnXKCG6YwMyyMe7DCf4fZzCNJEf9CCwLr Zu9wgPBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkI3v-009Vmw-9Q; Fri, 29 Apr 2022 04:16:59 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkI3r-009VmR-PA for linux-arm-kernel@lists.infradead.org; Fri, 29 Apr 2022 04:16:58 +0000 Received: from dggpemm500024.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4KqK1Z0Y7qzhYST; Fri, 29 Apr 2022 12:16:34 +0800 (CST) Received: from dggpemm500006.china.huawei.com (7.185.36.236) by dggpemm500024.china.huawei.com (7.185.36.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 29 Apr 2022 12:16:49 +0800 Received: from [10.174.178.55] (10.174.178.55) by dggpemm500006.china.huawei.com (7.185.36.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 29 Apr 2022 12:16:49 +0800 Subject: Re: [PATCH v2] arm64: add the printing of tpidr_elx in __show_regs() To: Will Deacon CC: Catalin Marinas , , , "James Morse" References: <20220316062408.1113-1-thunder.leizhen@huawei.com> <20220428102156.GA14123@willie-the-truck> <4c956c17-6e13-37a1-7da3-b2c8243c2c01@huawei.com> <20220428131259.GA14810@willie-the-truck> From: "Leizhen (ThunderTown)" Message-ID: Date: Fri, 29 Apr 2022 12:16:48 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20220428131259.GA14810@willie-the-truck> Content-Language: en-US X-Originating-IP: [10.174.178.55] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpemm500006.china.huawei.com (7.185.36.236) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220428_211656_210252_E13B61DC X-CRM114-Status: GOOD ( 21.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022/4/28 21:13, Will Deacon wrote: > On Thu, Apr 28, 2022 at 08:03:50PM +0800, Leizhen (ThunderTown) wrote: >> >> >> On 2022/4/28 19:07, Leizhen (ThunderTown) wrote: >>> >>> >>> On 2022/4/28 18:21, Will Deacon wrote: >>>> On Wed, Mar 16, 2022 at 02:24:08PM +0800, Zhen Lei wrote: >>>>> Commit 7158627686f0 ("arm64: percpu: implement optimised pcpu access >>>>> using tpidr_el1") and commit 6d99b68933fb ("arm64: alternatives: use >>>>> tpidr_el2 on VHE hosts") use tpidr_elx to cache my_cpu_offset to optimize >>>>> pcpu access. However, when performing reverse execution based on the >>>>> registers and the memory contents in kdump, this information is sometimes >>>>> required if there is a pcpu access. >>>>> >>>>> Signed-off-by: Zhen Lei >>>>> --- >>>>> arch/arm64/kernel/process.c | 11 +++++++++++ >>>>> 1 file changed, 11 insertions(+) >>>>> >>>>> v1 --> v2: >>>>> Directly print the tpidr_elx register of the current exception level. >>>>> Avoid coupling with the implementation of 'my_cpu_offset'. >>>>> >>>>> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >>>>> index 5369e649fa79ff8..738932e6fa4e947 100644 >>>>> --- a/arch/arm64/kernel/process.c >>>>> +++ b/arch/arm64/kernel/process.c >>>>> @@ -216,6 +216,17 @@ void __show_regs(struct pt_regs *regs) >>>>> show_regs_print_info(KERN_DEFAULT); >>>>> print_pstate(regs); >>>>> >>>>> + switch (read_sysreg(CurrentEL)) { >>>> >>>> This should use is_kernel_in_hyp_mode() to detect if we're running at El2. >> >> static inline bool is_kernel_in_hyp_mode(void) >> { >> return read_sysreg(CurrentEL) == CurrentEL_EL2; >> } >> >> I think it's more intuitive to use "switch (read_sysreg(CurrentEL))". > > No, I disagree with you here, sorry. OK. Change it to the following form in v3? + if (is_kernel_in_hyp_mode()) + printk("tpidr_el2 : %016llx\n", read_sysreg(TPIDR_EL2)); + else + printk("tpidr_el1 : %016llx\n", read_sysreg(TPIDR_EL1)); By the way, Is there a requirement on the case of register names? I see some use TPIDR_EL1 and some use tpidr_el1. > >>>>> + case CurrentEL_EL1: >>>>> + printk("tpidr_el1 : %016llx\n", read_sysreg(TPIDR_EL1)); >>>>> + break; >>>>> + case CurrentEL_EL2: >>>>> + printk("tpidr_el2 : %016llx\n", read_sysreg(TPIDR_EL2)); >>>>> + break; >>>>> + default: >>>>> + break; >>>>> + } >>>> >>>> I think this path can be triggered directly from usermode, so we really >>>> shouldn't be printing raw kernel virtual addresses here. >>> >>> I run echo c > /proc/sysrq-trigger and didn't trigger this path, but maybe >>> there's another way. Analysis from the other side, except for the instruction >>> address, all generic registers r0-r31 is output as raw. There's also an >>> opportunity to contain the instruction address. >> >> On second thought, there seemed to be nothing wrong with it. The user need >> to have capable() first. Then the address of the perpcu memory is not static, >> the memory is dynamically allocated, exposing it is no different than exposing sp. > > If show_unhandled_signals is set, then I think any fatal signal takes this > path, no? I looked at the implementation of arm64_show_signal(), and there must be a chance to take this path. But last night, I came to my senses, the value stored in tpidr is actually an offset, not an address. So there should be no kernel address leakage problem. > > Will > . > -- Regards, Zhen Lei _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel