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Fri, 8 Jan 2021 05:03:38 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 8 Jan 2021 05:03:38 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 8 Jan 2021 05:03:38 -0600 Received: from [10.250.235.36] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 108B3Zso052195; Fri, 8 Jan 2021 05:03:36 -0600 Subject: Re: [PATCH 4/7] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC To: Peter Rosin , Vinod Koul , Rob Herring , Nishanth Menon , Swapnil Jakhade References: <20201224114250.1083-1-kishon@ti.com> <20201224114250.1083-5-kishon@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Fri, 8 Jan 2021 16:33:34 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210108_060344_955426_CE97907B X-CRM114-Status: GOOD ( 18.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Peter, On 08/01/21 4:16 pm, Peter Rosin wrote: > Hi! > > On 2020-12-24 12:42, Kishon Vijay Abraham I wrote: >> AM64 has a single lane SERDES which can be configured to be used >> with either PCIe or USB. Define the possilbe values for the SERDES >> function in AM64 SoC here. >> >> Signed-off-by: Kishon Vijay Abraham I >> --- >> include/dt-bindings/mux/ti-serdes.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h >> index 9047ec6bd3cf..68e0f76deed1 100644 >> --- a/include/dt-bindings/mux/ti-serdes.h >> +++ b/include/dt-bindings/mux/ti-serdes.h >> @@ -90,4 +90,8 @@ >> #define J7200_SERDES0_LANE3_USB 0x2 >> #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 >> >> +/* AM64 */ > > In case you end up keeping these defines, despite the comment by Rob... > > Nitpick, the J721E and J7200 sections have a blank line here, between the > header comment and the actual defines. But mehh... > > Acked-by: Peter Rosin Sure, will fix it in the next revision. Thanks Kishon > > Cheers, > Peter > >> +#define AM64_SERDES0_LANE0_PCIE0 0x0 >> +#define AM64_SERDES0_LANE0_USB 0x1 >> + >> #endif /* _DT_BINDINGS_MUX_TI_SERDES */ >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel