* [v6 0/2] Add MediaTek MT8192 clock provider device nodes
@ 2021-07-27 2:32 Chun-Jie Chen
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
2021-07-27 2:32 ` [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Chun-Jie Chen
0 siblings, 2 replies; 10+ messages in thread
From: Chun-Jie Chen @ 2021-07-27 2:32 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group
This series is based on v5.14-rc1 and depends on [1].
change since v5:
- no change (rebased to 5.14)
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=521127
Chun-Jie Chen (2):
arm64: dts: mediatek: Add mt8192 clock controllers
arm64: dts: mediatek: Correct UART0 bus clock of MT8192
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++++++++++++++++++++++-
1 file changed, 164 insertions(+), 1 deletion(-)
base-commit: c977bba059550dba24ac6233b11c69f4edc1a968
prerequisite-patch-id: 82ced16215cdd31201c6146ddb5c30bc17525996
prerequisite-patch-id: 7f2137e77cfc439c2e4b4e4369a6d6b48fec1ece
prerequisite-patch-id: 15f52bb664f0f0436627d056a53afefb0b99f67a
prerequisite-patch-id: 479b44dfdc6d7b367c0d441d8635d2dc02466057
prerequisite-patch-id: 5df1858972e343d3750cdda1063655fc232eb831
prerequisite-patch-id: 7e63a29430f65c2a0d56d7353df884645d70ed8c
prerequisite-patch-id: 2a6200e8a05329d51aaa4fd63aacfbba66d16177
prerequisite-patch-id: 604d2702c4217b77de3dc305ff08f630ba38fdb4
prerequisite-patch-id: d3ece2688dbd45eee248a8c6ba3206c0c673c904
prerequisite-patch-id: 1bebe1cd9b267c974cae50c3df8c0f8f4f0b0b3d
prerequisite-patch-id: 3b34fe85667da5287bde9fd2378359be4a126266
prerequisite-patch-id: 5d3d139212ab304739b75f7638251703b95948d5
prerequisite-patch-id: 621291b21be177a63eaf6769aa6d2ee8ddb2ea2b
prerequisite-patch-id: 024f786586b409420782d24218b15f05f6476667
prerequisite-patch-id: 946aae93303bde26226289dc389c94de96a9dacd
prerequisite-patch-id: b3ddf6f2079c3c269bd24091243030a971c43cbc
prerequisite-patch-id: 5c0e0308aa8eb06ca6df6f5467bc925f2cc106ad
prerequisite-patch-id: d4e481acd8b970f08d3e4da9c8fc0ad6e1fff551
prerequisite-patch-id: 99db7309fbe1b9f73a07e25d5174db8976c77a2c
prerequisite-patch-id: cffbc99e9e60f6db43cf7879f17e05c5b041d312
--
2.18.0
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
2021-07-27 2:32 [v6 0/2] Add MediaTek MT8192 clock provider device nodes Chun-Jie Chen
@ 2021-07-27 2:32 ` Chun-Jie Chen
2021-07-28 6:09 ` Ikjoon Jang
` (2 more replies)
2021-07-27 2:32 ` [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Chun-Jie Chen
1 sibling, 3 replies; 10+ messages in thread
From: Chun-Jie Chen @ 2021-07-27 2:32 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group, Weiyi Lu,
Chun-Jie Chen
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9757138a8bbd..c7c7d4e017ae 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -257,6 +258,24 @@
};
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8192-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8192-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -282,6 +301,12 @@
#interrupt-cells = <2>;
};
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
@@ -291,6 +316,12 @@
clock-names = "clk13m";
};
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8192-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
@@ -311,6 +342,12 @@
status = "disabled";
};
+ imp_iic_wrap_c: clock-controller@11007000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_c";
+ reg = <0 0x11007000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@@ -436,6 +473,12 @@
status = "disable";
};
+ audsys: clock-controller@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
@@ -449,6 +492,12 @@
status = "disabled";
};
+ imp_iic_wrap_e: clock-controller@11cb1000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_e";
+ reg = <0 0x11cb1000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
@@ -488,6 +537,12 @@
status = "disabled";
};
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
@@ -527,6 +582,12 @@
status = "disabled";
};
+ imp_iic_wrap_ws: clock-controller@11d23000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_ws";
+ reg = <0 0x11d23000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
@@ -540,6 +601,12 @@
status = "disabled";
};
+ imp_iic_wrap_w: clock-controller@11e01000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_w";
+ reg = <0 0x11e01000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@@ -565,5 +632,101 @@
#size-cells = <0>;
status = "disabled";
};
+
+ imp_iic_wrap_n: clock-controller@11f02000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_n";
+ reg = <0 0x11f02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc_top: clock-controller@11f10000 {
+ compatible = "mediatek,mt8192-msdc_top";
+ reg = <0 0x11f10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc: clock-controller@11f60000 {
+ compatible = "mediatek,mt8192-msdc";
+ reg = <0 0x11f60000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8192-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15020000 {
+ compatible = "mediatek,mt8192-imgsys";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys2: clock-controller@15820000 {
+ compatible = "mediatek,mt8192-imgsys2";
+ reg = <0 0x15820000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1600f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1602f000 {
+ compatible = "mediatek,mt8192-vdecsys";
+ reg = <0 0x1602f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@17000000 {
+ compatible = "mediatek,mt8192-vencsys";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8192-camsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1a04f000 {
+ compatible = "mediatek,mt8192-camsys_rawa";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1a06f000 {
+ compatible = "mediatek,mt8192-camsys_rawb";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawc: clock-controller@1a08f000 {
+ compatible = "mediatek,mt8192-camsys_rawc";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@1b000000 {
+ compatible = "mediatek,mt8192-ipesys";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mdpsys: clock-controller@1f000000 {
+ compatible = "mediatek,mt8192-mdpsys";
+ reg = <0 0x1f000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2021-07-27 2:32 [v6 0/2] Add MediaTek MT8192 clock provider device nodes Chun-Jie Chen
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
@ 2021-07-27 2:32 ` Chun-Jie Chen
2021-07-28 6:14 ` Ikjoon Jang
1 sibling, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-07-27 2:32 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group, Weiyi Lu,
Chun-Jie Chen
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c7c7d4e017ae..9810f1d441da 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
@ 2021-07-28 6:09 ` Ikjoon Jang
2021-08-05 15:43 ` Matthias Brugger
2021-08-10 8:52 ` Matthias Brugger
2 siblings, 0 replies; 10+ messages in thread
From: Ikjoon Jang @ 2021-07-28 6:09 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support, srv_heupstream,
Project_Global_Chrome_Upstream_Group, Weiyi Lu
Hi,
On Tue, Jul 27, 2021 at 10:33 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add clock controller nodes for SoC mt8192
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
(snip)
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2021-07-27 2:32 ` [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Chun-Jie Chen
@ 2021-07-28 6:14 ` Ikjoon Jang
2021-07-30 2:43 ` Chun-Jie Chen
0 siblings, 1 reply; 10+ messages in thread
From: Ikjoon Jang @ 2021-07-28 6:14 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi,
On Tue, Jul 27, 2021 at 10:43 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> infra_uart0 clock is the real one what uart0 uses as bus clock.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index c7c7d4e017ae..9810f1d441da 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -327,7 +327,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x1000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
There're many other nodes still having only clk26m. Will you update them too?
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2021-07-28 6:14 ` Ikjoon Jang
@ 2021-07-30 2:43 ` Chun-Jie Chen
2021-08-05 15:44 ` Matthias Brugger
0 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-07-30 2:43 UTC (permalink / raw)
To: Ikjoon Jang
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Wed, 2021-07-28 at 14:14 +0800, Ikjoon Jang wrote:
> Hi,
>
> On Tue, Jul 27, 2021 at 10:43 AM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
> >
> > infra_uart0 clock is the real one what uart0 uses as bus clock.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index c7c7d4e017ae..9810f1d441da 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -327,7 +327,7 @@
> > "mediatek,mt6577-uart";
> > reg = <0 0x11002000 0 0x1000>;
> > interrupts = <GIC_SPI 109
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > - clocks = <&clk26m>, <&clk26m>;
> > + clocks = <&clk26m>, <&infracfg
> > CLK_INFRA_UART0>;
> > clock-names = "baud", "bus";
> > status = "disabled";
> > };
>
> There're many other nodes still having only clk26m. Will you update
> them too?
>
Others will be updated by IP owner.
Best Regards,
Chun-Jie
> > --
> > 2.18.0
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> >
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!1bIz6X2EiFbigCImzQmbqtezIFfl1LRBuPOYTqBdl5wfx8b-zp0zQP68R7RhaIcAAXXF$
> >
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
2021-07-28 6:09 ` Ikjoon Jang
@ 2021-08-05 15:43 ` Matthias Brugger
2021-08-10 8:52 ` Matthias Brugger
2 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2021-08-05 15:43 UTC (permalink / raw)
To: Chun-Jie Chen, Rob Herring, Nicolas Boichat, Stephen Boyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group, Weiyi Lu
On 27/07/2021 04:32, Chun-Jie Chen wrote:
> Add clock controller nodes for SoC mt8192
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9757138a8bbd..c7c7d4e017ae 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -5,6 +5,7 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/mt8192-clk.h>
I'd need a stable branch from Stephen to be able to take this one. Otherwise
we'll need to wait for v5.15-rc1 to be published before I can take them without
compile errors.
Regards,
Matthias
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -257,6 +258,24 @@
> };
> };
>
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8192-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10003000 {
> + compatible = "mediatek,mt8192-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> pio: pinctrl@10005000 {
> compatible = "mediatek,mt8192-pinctrl";
> reg = <0 0x10005000 0 0x1000>,
> @@ -282,6 +301,12 @@
> #interrupt-cells = <2>;
> };
>
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8192-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> systimer: timer@10017000 {
> compatible = "mediatek,mt8192-timer",
> "mediatek,mt6765-timer";
> @@ -291,6 +316,12 @@
> clock-names = "clk13m";
> };
>
> + scp_adsp: clock-controller@10720000 {
> + compatible = "mediatek,mt8192-scp_adsp";
> + reg = <0 0x10720000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> uart0: serial@11002000 {
> compatible = "mediatek,mt8192-uart",
> "mediatek,mt6577-uart";
> @@ -311,6 +342,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_c: clock-controller@11007000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_c";
> + reg = <0 0x11007000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> spi0: spi@1100a000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -436,6 +473,12 @@
> status = "disable";
> };
>
> + audsys: clock-controller@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c3: i2c3@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> @@ -449,6 +492,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_e: clock-controller@11cb1000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_e";
> + reg = <0 0x11cb1000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c7: i2c7@11d00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d00000 0 0x1000>,
> @@ -488,6 +537,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_s: clock-controller@11d03000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_s";
> + reg = <0 0x11d03000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c1: i2c1@11d20000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d20000 0 0x1000>,
> @@ -527,6 +582,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_ws: clock-controller@11d23000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_ws";
> + reg = <0 0x11d23000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c5: i2c5@11e00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11e00000 0 0x1000>,
> @@ -540,6 +601,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_w: clock-controller@11e01000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_w";
> + reg = <0 0x11e01000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c0: i2c0@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> @@ -565,5 +632,101 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + imp_iic_wrap_n: clock-controller@11f02000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_n";
> + reg = <0 0x11f02000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc_top: clock-controller@11f10000 {
> + compatible = "mediatek,mt8192-msdc_top";
> + reg = <0 0x11f10000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc: clock-controller@11f60000 {
> + compatible = "mediatek,mt8192-msdc";
> + reg = <0 0x11f60000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mfgcfg: clock-controller@13fbf000 {
> + compatible = "mediatek,mt8192-mfgcfg";
> + reg = <0 0x13fbf000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys: clock-controller@15020000 {
> + compatible = "mediatek,mt8192-imgsys";
> + reg = <0 0x15020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys2: clock-controller@15820000 {
> + compatible = "mediatek,mt8192-imgsys2";
> + reg = <0 0x15820000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys_soc: clock-controller@1600f000 {
> + compatible = "mediatek,mt8192-vdecsys_soc";
> + reg = <0 0x1600f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: clock-controller@1602f000 {
> + compatible = "mediatek,mt8192-vdecsys";
> + reg = <0 0x1602f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: clock-controller@17000000 {
> + compatible = "mediatek,mt8192-vencsys";
> + reg = <0 0x17000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: clock-controller@1a000000 {
> + compatible = "mediatek,mt8192-camsys";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawa: clock-controller@1a04f000 {
> + compatible = "mediatek,mt8192-camsys_rawa";
> + reg = <0 0x1a04f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawb: clock-controller@1a06f000 {
> + compatible = "mediatek,mt8192-camsys_rawb";
> + reg = <0 0x1a06f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawc: clock-controller@1a08f000 {
> + compatible = "mediatek,mt8192-camsys_rawc";
> + reg = <0 0x1a08f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + ipesys: clock-controller@1b000000 {
> + compatible = "mediatek,mt8192-ipesys";
> + reg = <0 0x1b000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mdpsys: clock-controller@1f000000 {
> + compatible = "mediatek,mt8192-mdpsys";
> + reg = <0 0x1f000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
> };
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2021-07-30 2:43 ` Chun-Jie Chen
@ 2021-08-05 15:44 ` Matthias Brugger
2021-08-11 12:12 ` Chun-Jie Chen
0 siblings, 1 reply; 10+ messages in thread
From: Matthias Brugger @ 2021-08-05 15:44 UTC (permalink / raw)
To: Chun-Jie Chen, Ikjoon Jang
Cc: Rob Herring, Nicolas Boichat,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On 30/07/2021 04:43, Chun-Jie Chen wrote:
> On Wed, 2021-07-28 at 14:14 +0800, Ikjoon Jang wrote:
>> Hi,
>>
>> On Tue, Jul 27, 2021 at 10:43 AM Chun-Jie Chen
>> <chun-jie.chen@mediatek.com> wrote:
>>>
>>> infra_uart0 clock is the real one what uart0 uses as bus clock.
>>>
>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index c7c7d4e017ae..9810f1d441da 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -327,7 +327,7 @@
>>> "mediatek,mt6577-uart";
>>> reg = <0 0x11002000 0 0x1000>;
>>> interrupts = <GIC_SPI 109
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> - clocks = <&clk26m>, <&clk26m>;
>>> + clocks = <&clk26m>, <&infracfg
>>> CLK_INFRA_UART0>;
>>> clock-names = "baud", "bus";
>>> status = "disabled";
>>> };
>>
>> There're many other nodes still having only clk26m. Will you update
>> them too?
>>
>
> Others will be updated by IP owner.
>
As it seems we will have some time before this can be merged, could you help
work with the other IP owners to get one big patch that updates all clocks?
Thanks a lot,
Matthias
> Best Regards,
> Chun-Jie
>
>>> --
>>> 2.18.0
>>> _______________________________________________
>>> Linux-mediatek mailing list
>>> Linux-mediatek@lists.infradead.org
>>>
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!1bIz6X2EiFbigCImzQmbqtezIFfl1LRBuPOYTqBdl5wfx8b-zp0zQP68R7RhaIcAAXXF$
>>>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
2021-07-28 6:09 ` Ikjoon Jang
2021-08-05 15:43 ` Matthias Brugger
@ 2021-08-10 8:52 ` Matthias Brugger
2 siblings, 0 replies; 10+ messages in thread
From: Matthias Brugger @ 2021-08-10 8:52 UTC (permalink / raw)
To: Chun-Jie Chen, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group, Weiyi Lu
On 27/07/2021 04:32, Chun-Jie Chen wrote:
> Add clock controller nodes for SoC mt8192
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Applied to v5.15-tmp/dst64
Please help making patch 2/2 better, adding clocks to all nodes.
Thanks a lot!
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9757138a8bbd..c7c7d4e017ae 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -5,6 +5,7 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/mt8192-clk.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -257,6 +258,24 @@
> };
> };
>
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8192-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10003000 {
> + compatible = "mediatek,mt8192-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> pio: pinctrl@10005000 {
> compatible = "mediatek,mt8192-pinctrl";
> reg = <0 0x10005000 0 0x1000>,
> @@ -282,6 +301,12 @@
> #interrupt-cells = <2>;
> };
>
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8192-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> systimer: timer@10017000 {
> compatible = "mediatek,mt8192-timer",
> "mediatek,mt6765-timer";
> @@ -291,6 +316,12 @@
> clock-names = "clk13m";
> };
>
> + scp_adsp: clock-controller@10720000 {
> + compatible = "mediatek,mt8192-scp_adsp";
> + reg = <0 0x10720000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> uart0: serial@11002000 {
> compatible = "mediatek,mt8192-uart",
> "mediatek,mt6577-uart";
> @@ -311,6 +342,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_c: clock-controller@11007000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_c";
> + reg = <0 0x11007000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> spi0: spi@1100a000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -436,6 +473,12 @@
> status = "disable";
> };
>
> + audsys: clock-controller@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c3: i2c3@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> @@ -449,6 +492,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_e: clock-controller@11cb1000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_e";
> + reg = <0 0x11cb1000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c7: i2c7@11d00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d00000 0 0x1000>,
> @@ -488,6 +537,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_s: clock-controller@11d03000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_s";
> + reg = <0 0x11d03000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c1: i2c1@11d20000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d20000 0 0x1000>,
> @@ -527,6 +582,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_ws: clock-controller@11d23000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_ws";
> + reg = <0 0x11d23000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c5: i2c5@11e00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11e00000 0 0x1000>,
> @@ -540,6 +601,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_w: clock-controller@11e01000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_w";
> + reg = <0 0x11e01000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c0: i2c0@11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> @@ -565,5 +632,101 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + imp_iic_wrap_n: clock-controller@11f02000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_n";
> + reg = <0 0x11f02000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc_top: clock-controller@11f10000 {
> + compatible = "mediatek,mt8192-msdc_top";
> + reg = <0 0x11f10000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc: clock-controller@11f60000 {
> + compatible = "mediatek,mt8192-msdc";
> + reg = <0 0x11f60000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mfgcfg: clock-controller@13fbf000 {
> + compatible = "mediatek,mt8192-mfgcfg";
> + reg = <0 0x13fbf000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys: clock-controller@15020000 {
> + compatible = "mediatek,mt8192-imgsys";
> + reg = <0 0x15020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys2: clock-controller@15820000 {
> + compatible = "mediatek,mt8192-imgsys2";
> + reg = <0 0x15820000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys_soc: clock-controller@1600f000 {
> + compatible = "mediatek,mt8192-vdecsys_soc";
> + reg = <0 0x1600f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: clock-controller@1602f000 {
> + compatible = "mediatek,mt8192-vdecsys";
> + reg = <0 0x1602f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: clock-controller@17000000 {
> + compatible = "mediatek,mt8192-vencsys";
> + reg = <0 0x17000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: clock-controller@1a000000 {
> + compatible = "mediatek,mt8192-camsys";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawa: clock-controller@1a04f000 {
> + compatible = "mediatek,mt8192-camsys_rawa";
> + reg = <0 0x1a04f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawb: clock-controller@1a06f000 {
> + compatible = "mediatek,mt8192-camsys_rawb";
> + reg = <0 0x1a06f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawc: clock-controller@1a08f000 {
> + compatible = "mediatek,mt8192-camsys_rawc";
> + reg = <0 0x1a08f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + ipesys: clock-controller@1b000000 {
> + compatible = "mediatek,mt8192-ipesys";
> + reg = <0 0x1b000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mdpsys: clock-controller@1f000000 {
> + compatible = "mediatek,mt8192-mdpsys";
> + reg = <0 0x1f000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
> };
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2021-08-05 15:44 ` Matthias Brugger
@ 2021-08-11 12:12 ` Chun-Jie Chen
0 siblings, 0 replies; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-11 12:12 UTC (permalink / raw)
To: Matthias Brugger, Ikjoon Jang
Cc: Rob Herring, Nicolas Boichat,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Mediatek SoC support, open list,
moderated list:ARM/Mediatek SoC support, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Thu, 2021-08-05 at 17:44 +0200, Matthias Brugger wrote:
>
> On 30/07/2021 04:43, Chun-Jie Chen wrote:
> > On Wed, 2021-07-28 at 14:14 +0800, Ikjoon Jang wrote:
> > > Hi,
> > >
> > > On Tue, Jul 27, 2021 at 10:43 AM Chun-Jie Chen
> > > <chun-jie.chen@mediatek.com> wrote:
> > > >
> > > > infra_uart0 clock is the real one what uart0 uses as bus clock.
> > > >
> > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index c7c7d4e017ae..9810f1d441da 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > @@ -327,7 +327,7 @@
> > > > "mediatek,mt6577-uart";
> > > > reg = <0 0x11002000 0 0x1000>;
> > > > interrupts = <GIC_SPI 109
> > > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > > - clocks = <&clk26m>, <&clk26m>;
> > > > + clocks = <&clk26m>, <&infracfg
> > > > CLK_INFRA_UART0>;
> > > > clock-names = "baud", "bus";
> > > > status = "disabled";
> > > > };
> > >
> > > There're many other nodes still having only clk26m. Will you
> > > update
> > > them too?
> > >
> >
> > Others will be updated by IP owner.
> >
>
> As it seems we will have some time before this can be merged, could
> you help
> work with the other IP owners to get one big patch that updates all
> clocks?
>
> Thanks a lot,
> Matthias
>
Ok, I will update all clock setting (uart/nor_flash/i2c/spi) in
mt8192.dtsi at the latest kernel version. Did you suggest to merge all
to one patch or separate to different patches but put in same
series?
Best Regards,
Chun-Jie
> > Best Regards,
> > Chun-Jie
> >
> > > > --
> > > > 2.18.0
> > > > _______________________________________________
> > > > Linux-mediatek mailing list
> > > > Linux-mediatek@lists.infradead.org
> > > >
> >
> >
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!1bIz6X2EiFbigCImzQmbqtezIFfl1LRBuPOYTqBdl5wfx8b-zp0zQP68R7RhaIcAAXXF$
> > > >
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-08-11 12:15 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-27 2:32 [v6 0/2] Add MediaTek MT8192 clock provider device nodes Chun-Jie Chen
2021-07-27 2:32 ` [v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
2021-07-28 6:09 ` Ikjoon Jang
2021-08-05 15:43 ` Matthias Brugger
2021-08-10 8:52 ` Matthias Brugger
2021-07-27 2:32 ` [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Chun-Jie Chen
2021-07-28 6:14 ` Ikjoon Jang
2021-07-30 2:43 ` Chun-Jie Chen
2021-08-05 15:44 ` Matthias Brugger
2021-08-11 12:12 ` Chun-Jie Chen
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