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Fri, 24 Jan 2020 13:57:09 +0100 (CET) Subject: Re: STM32MP1 level triggered interrupts To: Alexandre Torgue , Marc Zyngier , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= References: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> <65a1c5b2-c1b9-322f-338c-e6ff6379d8d1@denx.de> <129d04a0-c846-506d-5726-4a1024d977a6@st.com> <80db762c-3b3d-f007-2f9b-dadbffd95782@denx.de> <360b1adc-32f1-7993-c463-e52c7a5a8a67@st.com> <20200123101225.nscpc5t4nmlarbw2@pengutronix.de> <03fd1cb7b5985b3221f66c6b0058adc8@kernel.org> <20200123105214.ru4j76xbisjtbtgw@pengutronix.de> From: Marek Vasut Message-ID: Date: Fri, 24 Jan 2020 13:25:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200124_045713_677690_CE45B79A X-CRM114-Status: GOOD ( 15.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux ARM , Maxime Coquelin , Patrick Delaunay , linux-stm32@st-md-mailman.stormreply.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/24/20 10:17 AM, Alexandre Torgue wrote: [...] >>>>> Doing this kind of tricks in 2020 is pretty poor for a modern SoC. >>>> >>>> With the above assumption given, I think that is ok even in 2020. >>>> (But I >>>> wonder about SoCs in 2020 not being able to handle level sensitive irqs >>>> :-) >>> >>> Quite. Seems incredibly restrictive, and very unfortunate. >> >> So I wonder, the EXTI should be able to read the GPIO line which caused >> the interrupt when the interrupt handler returns, and trigger the >> interrupt again if the line is still low. This might need some phandle >> from the EXTI to GPIO bank in DT, but should be generally doable, no ? >> It's a crutch all right. >> >> But I still wonder, what is the purpose of the EXTImux in that SoC? >> Shouldn't that permit routing GPIOs directly into GIC SPIs, which would >> then permit detecting at least level-high interrupts ? >> > > For this SoC, EXTI block detects external line edges and rises a GIC SPI > interrupt. This EXTi block is mainly used to handle HW events like > buttons, clocks ... So first issue seems more to be a design issue (your > design doesn't fit with MP1 datasheet). I am asking about the EXTImux block, see the DM00327659 datasheet section 24.2 EXTI block diagram , figure 140 and exti[15:0] . Maybe that permits routing external events directly to GIC SPIs ? > Now, let's find a solution. I'll have a look on your proposition: "check > the line in EOI callback and retrig". That could probably work. > Marc, this kind a solution could be acceptable on your side ? > > regards > Alex > > > > > -- Best regards, Marek Vasut _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel