From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Tinghan Shen <tinghan.shen@mediatek.com>,
Bjorn Andersson <andersson@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Tiffany Lin <tiffany.lin@mediatek.com>,
Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
Yunfei Dong <yunfei.dong@mediatek.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org
Subject: Re: [PATCH v3 03/11] arm64: dts: mt8195: Add SCP core 1 node
Date: Tue, 27 Sep 2022 13:01:09 +0200 [thread overview]
Message-ID: <cbed65b6-bd7c-b750-ac8e-504fe143a804@collabora.com> (raw)
In-Reply-To: <20220927025606.26673-4-tinghan.shen@mediatek.com>
Il 27/09/22 04:55, Tinghan Shen ha scritto:
> Add the 2nd core(core 1) of MT8195 dual-core SCP to devicetree file.
> Reserve some SRAM spaces for the core 1 image.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..48d457bd39b8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -760,12 +760,24 @@
>
> scp: scp@10500000 {
> compatible = "mediatek,mt8195-scp";
> - reg = <0 0x10500000 0 0x100000>,
> + reg = <0 0x10500000 0 0xa0000>,
> <0 0x10720000 0 0xe0000>,
> <0 0x10700000 0 0x8000>;
> reg-names = "sram", "cfg", "l1tcm";
> interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
> status = "disabled";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x105a0000 0 0x105a0000 0x20000>;
> +
> + scp_c1: scp-c1@105a0000 {
> + compatible = "mediatek,mt8195-scp-core";
> + reg = <0x105a0000 0x20000>;
> + reg-names = "sram";
> + interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
> + status = "disabled";
> + };
I think that the best way of describing a dual-core SCP in devicetree would
be either something like:
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0xa0000>, <0 0x105a0000 0 0x20000>,
<0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>;
reg-names = "sram", "sram-c1", "cfg", "l1tcm";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
...but that may pose an issue when trying to assign different (or more instances
of the same) subnode(s) to each core... for which, I'd be more for something like:
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>;
reg-names = "cfg", "l1tcm";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10500000 0x100000>;
status = "disabled";
scp_c0: scp-core@0 {
compatible = "mediatek,mt8195-scp-core";
reg = <0x0 0xa0000>;
reg-names = "sram";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
};
scp_c1: scp-core@a0000 {
compatible = "mediatek,mt8195-scp-core";
reg = <0xa0000 0x20000>;
reg-names = "sram";
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
};
};
Regards,
Angelo
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next prev parent reply other threads:[~2022-09-27 11:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 2:55 [PATCH v3 00/11] Add support for MT8195 SCP 2nd core Tinghan Shen
2022-09-27 2:55 ` [PATCH v3 01/11] dt-bindings: remoteproc: mediatek: Give the subnode a persistent name Tinghan Shen
2022-09-28 6:54 ` Peng Fan
2022-09-28 17:47 ` Krzysztof Kozlowski
2022-09-27 2:55 ` [PATCH v3 02/11] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Tinghan Shen
2022-09-28 7:01 ` Peng Fan
2022-09-28 9:17 ` TingHan Shen (沈廷翰)
2022-09-28 9:37 ` Peng Fan
2022-09-28 17:50 ` Krzysztof Kozlowski
2022-09-28 17:48 ` Krzysztof Kozlowski
2022-09-27 2:55 ` [PATCH v3 03/11] arm64: dts: mt8195: Add SCP core 1 node Tinghan Shen
2022-09-27 11:01 ` AngeloGioacchino Del Regno [this message]
2023-01-17 8:19 ` TingHan Shen (沈廷翰)
2023-01-17 8:55 ` AngeloGioacchino Del Regno
2022-09-27 2:55 ` [PATCH v3 04/11] remoteproc: mediatek: Remove redundant rproc_boot Tinghan Shen
2022-09-27 11:03 ` AngeloGioacchino Del Regno
2022-09-28 8:27 ` TingHan Shen (沈廷翰)
2022-09-28 9:40 ` Peng Fan
2022-09-28 10:14 ` TingHan Shen (沈廷翰)
2022-09-27 2:56 ` [PATCH v3 05/11] remoteproc: mediatek: Add SCP core 1 register definitions Tinghan Shen
2022-09-27 11:04 ` AngeloGioacchino Del Regno
2022-09-27 2:56 ` [PATCH v3 06/11] remoteproc: mediatek: Add MT8195 SCP core 1 operations Tinghan Shen
2022-09-27 2:56 ` [PATCH v3 07/11] remoteproc: mediatek: Probe MT8195 SCP core 1 Tinghan Shen
2022-09-27 2:56 ` [PATCH v3 08/11] remoteproc: mediatek: Control SCP core 1 boot by rproc subdevice Tinghan Shen
2022-09-27 2:56 ` [PATCH v3 09/11] remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset Tinghan Shen
2022-09-27 2:56 ` [PATCH v3 10/11] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Tinghan Shen
2022-09-27 2:56 ` [PATCH v3 11/11] remoteproc: mediatek: Refine ipi handler error message Tinghan Shen
2022-09-27 11:06 ` AngeloGioacchino Del Regno
2022-11-01 20:40 ` [PATCH v3 00/11] Add support for MT8195 SCP 2nd core Mathieu Poirier
2023-01-17 7:43 ` TingHan Shen (沈廷翰)
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