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* [PATCH v1 00/50] Exynos5x clocks and buses changes
       [not found] <CGME20190715124433eucas1p2a292f236ea55751117836742c1ca5d23@eucas1p2.samsung.com>
@ 2019-07-15 12:43 ` Lukasz Luba
       [not found]   ` <CGME20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c@eucas1p2.samsung.com>
                     ` (49 more replies)
  0 siblings, 50 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Hi all,

The patch set fixes clock settings for the Exynos5420/5422/5800 SoCs which
can be found in Odroid XU3/4, Google Peach Pi. Support for DT board files
with Exynos5420 (like Google Peach Pit) are under development.  The old
implementation did not configure properly the clock rates or the
connections which could cause performance issues or instability.  The
Exynos5x SoC has complex clocks topology. Some of the NoC clock branches
provide clock to the device internal buses or AXI interface and had wrong
settings.

In the old configuration the OPP values where not reflecting the actually
set frequencies, which were possible by setting the divider value on the
clock tree. The algorithms in governors, which use these frequencies,
relied on wrong assumption during their calculations. It also applies to
device drivers code, which does not check the rate of the clock but relay
on OPP values, which in some cases are different.  It is not only the bus
frequency but also the connected component internal buses (accelerators
like e.g. G2D, scaler, rotator) frequency.  Wrong frequency set due to
impossible division from PLL rate caused that some devices had lower than
possible clock for internal logic and for the AXI bus which transfers the
data.  For example fixes for MMC controller, where OPP max frequency
changed from 150MHz to 240MHz, changing the PLL rate to proper value caused
performance increase up to 20% (FSYS2 OPP table).

Affected components inside SoC: image rotator, usb3.0 and 2.0 controller,
jpeg accelerator, image/video scaler, mmc controller, ISP, display
controller, all NoC buses.

Some of the clocks have name which might indicate their max speed, e.g.
CLK_DOUT_ACLK266 but it is not true.  The max speed clock from this example
is 300MHz (according to the RM) and has been reflected accordingly in this
patch set.

Main changes:
- defined new clocks or added IDs to take them from DT nodes
- set proper PLLs frequency for: MPLL, DPLL, which would handle children
  clock requirements down in the tree,
- changed parents of some clocks to proper PLL or to proper parent clock,
- properly calculated OPP values for the buses keeping in mind the parent
  clock frequency and possible values derived from there by one clock
divider with proper bit length indicating maximum allowed divider; thanks
to that it is possible to set the requested frequency in all children
without changing the PLL frequency, which also makes the governor frequency
values assumption true,
- some OPPs were removed because it was not possible to set them due to
  different base frequency, which would require of changing PLL rate, which
might affect other devices connected to this PLL and their misscalculated
rates.

The last two patches touches Exynos5800 and are optional. They have been
checked due to some issues with disabling parent, which accidently was
populated up to MPLL and shut down the PLL. They might be used for testing
on Peach Pi.

The patch set is based on Samsung clock repo and branch 'for-v5.3/next'
[1].

Regards,
Lukasz Luba

[1] https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git/log/?h=for-v5.3/next

Lukasz Luba (50):
  clk: samsung: add new IDs for Exynos5420 clocks
  clk: samsung: add IDs for Exynos5420 NoC clocks
  clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
  clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
  clk: samsung: add IDs to aclk400_isp in Exynos5420
  clk: samsung: add IDs to ACLK266 clocks in Exynos5420
  clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
  clk: samsung: change aclk266_isp clocks definitions Exynos5420
  clk: samsung: add IDs to FSYS clocks in Exynos5x
  clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
  clk: samsung: add IDs to UART clocks in Exynos5420
  clk: add ID to PWM MUX in Exynos5420
  clk: samsung: add DPLL rate table in Exynos5420
  clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
  clk: samsung: add MPLL rate table in Exynos5420
  clk: samsung: add SPLL rate table in Exynos5420
  clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
  ARM: dts: exynos: add bus_isp with OPP table
  ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
  ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
  ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
  ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
  ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
  ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
  ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
  ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
  ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
  ARM: dts: exynos: add bus_isp266 into Exynos5800
  ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
  ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
  ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
  ARM: dts: exynos: set parent clocks to PWM in Exynos5420
  ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
  ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
  ARM: dts: exynos: add bus_isp in Exynos5422
  ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
  ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
  ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
  ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
  ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
  ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
  ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi

 arch/arm/boot/dts/exynos5420.dtsi             | 116 +++++++-----
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  74 ++++++++
 arch/arm/boot/dts/exynos5800-peach-pi.dts     | 175 ++++++++++++++++++
 arch/arm/boot/dts/exynos5800.dtsi             |  10 +
 drivers/clk/samsung/clk-exynos5420.c          | 109 +++++++----
 include/dt-bindings/clock/exynos5420.h        |  27 ++-
 6 files changed, 429 insertions(+), 82 deletions(-)

-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks
       [not found]   ` <CGME20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-16  9:49       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

There is a need of new IDs which will be used for modeling proper hierarchy
in the Exynos54xx SoCs. Previous implementation rely on bootloader
settings, which are not configuring properly some clocks.
These IDs provide interface to set proper parents.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 include/dt-bindings/clock/exynos5420.h | 27 +++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 02d5ac469a3d..c37a28eeaf7e 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -230,6 +230,30 @@
 #define CLK_MOUT_USER_MAU_EPLL	659
 #define CLK_MOUT_SCLK_SPLL	660
 #define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
+#define CLK_MOUT_ACLK400_WCORE		662
+#define CLK_MOUT_SCLK_DPLL	663
+#define CLK_MOUT_ACLK100_NOC	664
+#define CLK_MOUT_ACLK200_FSYS2	665
+#define CLK_MOUT_PCLK200_FSYS	666
+#define CLK_MOUT_ACLK200_FSYS	667
+#define CLK_MOUT_ACLK400_ISP	668
+#define CLK_MOUT_ACLK400_MSCL	669
+#define CLK_MOUT_SCLK_MPLL	700
+#define CLK_MOUT_ACLK266	701
+#define CLK_MOUT_UART0		702
+#define CLK_MOUT_UART1		703
+#define CLK_MOUT_UART2		704
+#define CLK_MOUT_UART3		705
+#define CLK_MOUT_SCLK_CPLL	706
+#define CLK_MOUT_PWM		707
+#define CLK_MOUT_ACLK266_G2D		708
+#define CLK_MOUT_SW_ACLK400_WCORE	709
+#define CLK_MOUT_SW_ACLK400_MSCL	710
+#define CLK_MOUT_SW_ACLK400_ISP		711
+#define CLK_MOUT_SW_ACLK266_ISP		712
+#define CLK_MOUT_USER_ACLK266_ISP	713
+#define CLK_MOUT_ACLK266_ISP	714
+#define CLK_MOUT_MMC0		715
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
@@ -264,8 +288,9 @@
 #define CLK_FF_DOUT_SPLL2	797
 #define CLK_DOUT_PCLK_DREX0	798
 #define CLK_DOUT_PCLK_DREX1	799
+#define CLK_DOUT_ACLK266_ISP	800
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		800
+#define CLK_NR_CLKS		801
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks
       [not found]   ` <CGME20190715124435eucas1p2099cd7670a3d85d9b11eb0ff86041a2a@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-16  9:26       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The patch adds NoC WCORE clock IDs needed used for changing parent of the
main NoC clock from the DT device.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 16ad498e3f3f..d353870e7fda 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -463,7 +463,8 @@ static const struct samsung_fixed_factor_clock
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
 	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
-	MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
+	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
+			SRC_TOP0, 16, 3),
 	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
 
 	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
-	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
+	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
+			SRC_TOP0, 16, 2),
 	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 
 	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
@@ -674,8 +676,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 			SRC_TOP10, 8, 1),
 	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 			SRC_TOP10, 12, 1),
-	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
-			SRC_TOP10, 16, 1),
+	MUX(CLK_MOUT_SW_ACLK400_WCORE, "mout_sw_aclk400_wcore",
+			mout_sw_aclk400_wcore_p, SRC_TOP10, 16, 1),
 	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 			SRC_TOP10, 20, 1),
 	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
       [not found]   ` <CGME20190715124436eucas1p28a581bc25f6dae52a5b9b1af26d26368@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-16  9:13       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Change parent of dout_aclk400_wcore to mout_aclk400_wcore which reflects
topology described in the RM.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index d353870e7fda..361ee53fc9fc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -577,7 +577,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
 	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
-			"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
+			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
 };
 
 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
       [not found]   ` <CGME20190715124437eucas1p1827d7b5d7196f060799e5df6c27d29ad@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-16  9:17       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add needed IDs to MUXes which are used from DT to properly set clock
hierarchy.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 361ee53fc9fc..8f1d39cb2f1e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
 
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
-	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
+	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
+			SRC_TOP0, 4, 3),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
 			SRC_TOP0, 16, 3),
 	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 				TOP_SPARE2, 4, 1),
 
 	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
-	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
+	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
+			SRC_TOP0, 4, 2),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
 			SRC_TOP0, 16, 2),
 	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 
 	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 			SRC_TOP10, 0, 1),
-	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
-			SRC_TOP10, 4, 1),
+	MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
+			mout_sw_aclk400_mscl_p,	SRC_TOP10, 4, 1),
 	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
 			SRC_TOP10, 8, 1),
 	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 05/50] clk: samsung: add IDs to aclk400_isp in Exynos5420
       [not found]   ` <CGME20190715124437eucas1p2d817f0c1fcf4b523c7910218a6e557d9@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add clock IDs to MUXes related to ACLK400_ISP for managing them from DT
devices.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 8f1d39cb2f1e..74276875bc3e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -461,7 +461,8 @@ static const struct samsung_fixed_factor_clock
 };
 
 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
-	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
+	MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group3_5800_p,
+			SRC_TOP0, 0, 3),
 	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
 			SRC_TOP0, 4, 3),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
 				TOP_SPARE2, 4, 1),
 
-	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
+	MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group1_p,
+			SRC_TOP0, 0, 2),
 	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
 			SRC_TOP0, 4, 2),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
-	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
-			SRC_TOP10, 0, 1),
+	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
+			mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
 	MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
 			mout_sw_aclk400_mscl_p,	SRC_TOP10, 4, 1),
 	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 06/50] clk: samsung: add IDs to ACLK266 clocks in Exynos5420
       [not found]   ` <CGME20190715124438eucas1p2ee9d27c451eb7125bd3ec874baf76e14@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add IDs to MUXes related to ACLK266 for managing them from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 74276875bc3e..9b4a1d81f708 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -472,7 +472,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 	MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
 	MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
-	MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
+	MUX(CLK_MOUT_ACLK266, "mout_aclk266", mout_group5_5800_p,
+			SRC_TOP1, 20, 2),
 	MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
 
 	MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
@@ -561,7 +562,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 				SRC_TOP1, 4, 2),
 	MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
-	MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
+	MUX(CLK_MOUT_ACLK266, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 	MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 
 	MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 07/50] clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
       [not found]   ` <CGME20190715124439eucas1p18c4f512d2647717d77666d94dca867a6@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add IDs to MUXes of ACLK266_G2D to manage them from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9b4a1d81f708..9d54856dbcda 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -478,7 +478,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 
 	MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
 	MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
-	MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
+	MUX(CLK_MOUT_ACLK266_G2D, "mout_aclk266_g2d", mout_group5_5800_p,
+			SRC_TOP2, 12, 2),
 	MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
 	MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 	MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
@@ -567,7 +568,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 	MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
 	MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
-	MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
+	MUX(CLK_MOUT_ACLK266_G2D, "mout_aclk266_g2d", mout_group1_p,
+			SRC_TOP2, 12, 2),
 	MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420
       [not found]   ` <CGME20190715124440eucas1p10bb25e412f32f0da95761f96831893e6@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-16 10:22       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The ACLK266_ISP has different topology in Exynos5420 and 5422/5800.  In
Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
it takes the clock from 2-level mux from ACLK266.  In Exynos5422 there is a
dedicated clock tree and the PLL can be chosen.  The patch adds needed
MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d54856dbcda..5f251279b4c8 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
 PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
 					"mout_sclk_mpll", "ff_dout_spll2",
 					"mout_sclk_spll", "mout_sclk_epll"};
+PNAME(mout_group17_5800_p)	= { "dout_aclk266_isp", "dout_sclk_sw" };
+PNAME(mout_group18_5800_p)	= { "dout_osc_div", "mout_sw_aclk266_isp" };
+PNAME(mout_group19_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
+					"mout_sclk_mpll", "mout_sclk_ipll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock
@@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 
+	MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
+			SRC_TOP8, 12, 2),
 	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
 	MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
 	MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
@@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 
 	MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
 			SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
+	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+			mout_group18_5800_p, SRC_TOP9, 12, 1),
 	MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
 							SRC_TOP9, 16, 1),
 	MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 	MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
 							SRC_TOP9, 28, 1),
 
+	MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
+			SRC_TOP13, 12, 1),
 	MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
 	MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
 							SRC_TOP13, 20, 1),
@@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
 	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+	DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
+				DIV_TOP8, 12, 3),
 	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
 				DIV_TOP8, 16, 3),
 	DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
@@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 
+	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+			mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
+
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 			mout_group5_5800_p, SRC_TOP7, 16, 2),
 	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
@@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 			SRC_TOP4, 8, 1),
 	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 			SRC_TOP4, 12, 1),
-	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
-			SRC_TOP4, 16, 1),
 	MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 	MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x
       [not found]   ` <CGME20190715124441eucas1p12e1f58587318219a5a2c695faa200b17@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add IDs to MUXes of ACLK200_FSYS, ACLK_FSYS2, PCLK200_FSYS to manage them
from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 5f251279b4c8..6164d0ca75e0 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -622,9 +622,12 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
-	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
-	MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
-	MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
+	MUX(CLK_MOUT_ACLK200_FSYS2, "mout_aclk200_fsys2", mout_group1_p,
+			SRC_TOP0, 12, 2),
+	MUX(CLK_MOUT_PCLK200_FSYS, "mout_pclk200_fsys", mout_group1_p,
+			SRC_TOP0, 24, 2),
+	MUX(CLK_MOUT_ACLK200_FSYS, "mout_aclk200_fsys", mout_group1_p,
+			SRC_TOP0, 28, 2),
 
 	MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 	MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
       [not found]   ` <CGME20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-16 10:01       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The ACLK100_NOC has different topology in Exynos5420 and 5422/5800.  In
Exynos5420 this clock divider has 3 bits while in 5422/5800 has 4 bits.
The patch adds needed dividers in the exynos5800_div_clks, updates
exynos5x_div_clks and exynos5420_div_clks properly. It also adds IDs to
manage clocks from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6164d0ca75e0..c13f34d3d9a1 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -471,7 +471,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 			SRC_TOP0, 4, 3),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
 			SRC_TOP0, 16, 3),
-	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
+	MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_5800_p,
+			SRC_TOP0, 20, 2),
 
 	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 	MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
@@ -534,6 +535,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
 	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+				DIV_TOP0, 20, 4),
 	DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
 				DIV_TOP8, 12, 3),
 	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
@@ -569,7 +572,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 			SRC_TOP0, 4, 2),
 	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
 			SRC_TOP0, 16, 2),
-	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+	MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p,
+			SRC_TOP0, 20, 2),
 
 	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
@@ -600,6 +604,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
 	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+			DIV_TOP0, 20, 3),
 };
 
 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
@@ -798,8 +804,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 			DIV_TOP0, 8, 3),
 	DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
 			DIV_TOP0, 12, 3),
-	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
-			DIV_TOP0, 20, 3),
 	DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
 			DIV_TOP0, 24, 3),
 	DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420
       [not found]   ` <CGME20190715124442eucas1p197b23d50f6986477467d23f53b84d187@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add IDs to MUXes for UART to manage them from DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c13f34d3d9a1..7bf74401c4e7 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -768,10 +768,10 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 
 	/* PERIC Block */
-	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
-	MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
-	MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
-	MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+	MUX(CLK_MOUT_UART0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+	MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+	MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+	MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 12/50] clk: add ID to PWM MUX in Exynos5420
       [not found]   ` <CGME20190715124443eucas1p1adf02a02bf77448f2277ddd5fe5e895b@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add ID to PWM MUX to manage it from DT to reflect proper topology.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7bf74401c4e7..7f8221527633 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -772,7 +772,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 	MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 	MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
-	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+	MUX(CLK_MOUT_PWM, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 13/50] clk: samsung: add DPLL rate table in Exynos5420
       [not found]   ` <CGME20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-16  9:31       ` Chanwoo Choi
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The DPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the DPLL gets rate table the same for the
whole  PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the DPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7f8221527633..2395b02ce8c5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
 			CLK_SET_RATE_PARENT, 0),
-	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+	MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
+			SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
 	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
 	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
@@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
 
 	if (_get_rate("fin_pll") == 24 * MHZ) {
 		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+		exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
 		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 	}
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
       [not found]   ` <CGME20190715124445eucas1p1a73385fcbe6205d868ae63b1198ff572@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add ID to mout_sclk_cpll MUX to make possible children connection in
the DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2395b02ce8c5..6d1a0ef9172e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -696,7 +696,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 			CLK_SET_RATE_PARENT, 0),
 	MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
 			SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
-	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+	MUX(CLK_MOUT_SCLK_CPLL, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
 	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
 			mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 15/50] clk: samsung: add MPLL rate table in Exynos5420
       [not found]   ` <CGME20190715124446eucas1p1de55fe42ed5555c7a09b10f8c3ec3c3e@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The MPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the MPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the MPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_MPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6d1a0ef9172e..cded46f360f1 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -687,7 +687,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
 			mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 
-	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
+	MUX_F(CLK_MOUT_SCLK_MPLL, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1,
+			CLK_IS_CRITICAL, 0),
 	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
 	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
@@ -1518,6 +1519,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
 		exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
 		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+		exynos5x_plls[mpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 	}
 
 	if (soc == EXYNOS5420)
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 16/50] clk: samsung: add SPLL rate table in Exynos5420
       [not found]   ` <CGME20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The MPLL has fixed frequency left by the bootloader and it is not possible
to change it. With this patch the SPLL gets rate table the same for the
whole PLL family (similar as APLL, KPLL according to RM) so the frequency
might be changed to one of the values defined there.
It is needed for further patches which change the MPLL frequency to feed
the clocks with proper base.
It also sets CLK_IS_CRITICAL for SCLK_SPLL due to some drivers which could
disable master clock, which is then populated higher and tries to disable
PLL, which casues system crash. The flag is needed for this kind of use
cases.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index cded46f360f1..ead569a164cf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -690,7 +690,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX_F(CLK_MOUT_SCLK_MPLL, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1,
 			CLK_IS_CRITICAL, 0),
 	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
-	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+	MUX_F(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1,
+			CLK_IS_CRITICAL, 0),
 	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -1520,6 +1521,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
 		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
 		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 		exynos5x_plls[mpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+		exynos5x_plls[spll].rate_table = exynos5420_pll2550x_24mhz_tbl;
 	}
 
 	if (soc == EXYNOS5420)
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 17/50] clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
       [not found]   ` <CGME20190715124447eucas1p143a857f619f48b9b87437ec3b13dfb3f@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add ID to mout_mmc0 MUX to make possible children connection in
the DT.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ead569a164cf..8d58801baf2c 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -763,7 +763,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 
 	/* FSYS Block */
 	MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
-	MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+	MUX(CLK_MOUT_MMC0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 	MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 18/50] ARM: dts: exynos: add bus_isp with OPP table
       [not found]   ` <CGME20190715124448eucas1p1b3a8d16d6f5e9fd4ed49c3b7fa66e18e@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add bus_isp which controls ACLK400_ISP clock. The OPPs are aligned to
parent clock and PLL rate so that the PLL would not need to be
reprogrammed.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..1b717c5c3b1a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1095,6 +1095,14 @@
 			status = "disabled";
 		};
 
+		bus_isp: bus_isp {
+			compatible = "samsung,exynos-bus";
+			clocks = <&clock CLK_DOUT_ACLK400_ISP>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_isp_opp_table>;
+			status = "disabled";
+		};
+
 		bus_wcore_opp_table: opp_table2 {
 			compatible = "operating-points-v2";
 
@@ -1337,6 +1345,23 @@
 				opp-hz = /bits/ 64 <400000000>;
 			};
 		};
+
+		bus_isp_opp_table: opp_table17 {
+			compatible = "operating-points-v2";
+
+			opp00 {
+				opp-hz = /bits/ 64 <150000000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <200000000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
+		};
 	};
 
 	thermal-zones {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 19/50] ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
       [not found]   ` <CGME20190715124449eucas1p130d853368cb8bf02bef337da2d513fff@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The OPPs values for FSYS2 does not reflect the real possible frequencies.
According to the documentation the maximum frequency is 240MHz. This clock
is important to MMC controller controlling the AXI data bus speed and
internal buses. The new OPP values are aligned to parent PLL rate so that
there is no need of reprogramming PLL and the integer values are possible
to get using only a clock divider.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1b717c5c3b1a..941c58bdd809 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1161,13 +1161,13 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <75000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <100000000>;
+				opp-hz = /bits/ 64 <200000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <150000000>;
+				opp-hz = /bits/ 64 <240000000>;
 			};
 		};
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
       [not found]   ` <CGME20190715124450eucas1p189043d196375aa6adacf898de81bfa9b@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17  8:39       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The FSYS and FSYS2 buses have similar characteristics and both have max
frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
only to FSYS APB bus because APB max frequency is 200MHz.
The new OPPs for FSYS should increase its performance and related devices.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 941c58bdd809..c7fc4b829b2a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -995,7 +995,7 @@
 			compatible = "samsung,exynos-bus";
 			clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
 			clock-names = "bus";
-			operating-points-v2 = <&bus_fsys_apb_opp_table>;
+			operating-points-v2 = <&bus_fsys_opp_table>;
 			status = "disabled";
 		};
 
@@ -1003,7 +1003,7 @@
 			compatible = "samsung,exynos-bus";
 			clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
 			clock-names = "bus";
-			operating-points-v2 = <&bus_fsys2_opp_table>;
+			operating-points-v2 = <&bus_fsys_opp_table>;
 			status = "disabled";
 		};
 
@@ -1157,7 +1157,7 @@
 			};
 		};
 
-		bus_fsys2_opp_table: opp_table5 {
+		bus_fsys_opp_table: opp_table5 {
 			compatible = "operating-points-v2";
 
 			opp00 {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
       [not found]   ` <CGME20190715124451eucas1p2904b49f59cca0cbbc22381f168affbb5@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17  8:48       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add an OPP for FSYS APB which reflects the real possible frequency.
The bus will have a new parent clock which speed has 600MHz, thus
a new possible frequency provided by the clock divider is 150MHz.
According to the documentation max possible frequency for this bus is
200MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c7fc4b829b2a..2b36c2f77a10 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1153,6 +1153,9 @@
 				opp-hz = /bits/ 64 <100000000>;
 			};
 			opp01 {
+				opp-hz = /bits/ 64 <150000000>;
+			};
+			opp02 {
 				opp-hz = /bits/ 64 <200000000>;
 			};
 		};
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 22/50] ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
       [not found]   ` <CGME20190715124451eucas1p28ac87fa7bd7e602ffab69a6915f37536@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Update the bus_disp1 OPPs and add 400MHz which is max frequency for this
bus. The frequencies are aligned to parent clock such that it is not
needed to change the PLL rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2b36c2f77a10..6e82ffcbeacd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1305,7 +1305,7 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <120000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
 				opp-hz = /bits/ 64 <200000000>;
@@ -1313,6 +1313,9 @@
 			opp02 {
 				opp-hz = /bits/ 64 <300000000>;
 			};
+			opp03 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
 		};
 
 		bus_gscl_opp_table: opp_table15 {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
       [not found]   ` <CGME20190715124452eucas1p294d89255359b2036b19213427f558dbf@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17  9:08       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The lowest OPP must be aligned to possible value after division of parent
clock rate. Thus, change it to the value which is true for clock 1200MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 6e82ffcbeacd..0739e7bd4628 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1294,7 +1294,7 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <120000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
 				opp-hz = /bits/ 64 <200000000>;
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
       [not found]   ` <CGME20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The OPPs must reflect possible values after dividing the master clock.
The old values 400 and 333, 222, etc does not have common parent rate.
Thus, align the values to parent rate such that they will be set exactly
using only a divider.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0739e7bd4628..74d014f3eaa6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1336,18 +1336,15 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <84000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <167000000>;
+				opp-hz = /bits/ 64 <200000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <222000000>;
+				opp-hz = /bits/ 64 <300000000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <333000000>;
-			};
-			opp04 {
 				opp-hz = /bits/ 64 <400000000>;
 			};
 		};
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
       [not found]   ` <CGME20190715124454eucas1p1cd37552b222539b02629cb52e646ae29@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17 10:04       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

According to the documentation max frequency for ACLK300_DISP1 is 300MHz.
Add an OPP which makes it possible to use the full performance when needed.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 74d014f3eaa6..1097fa758d9e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1299,6 +1299,9 @@
 			opp01 {
 				opp-hz = /bits/ 64 <200000000>;
 			};
+			opp02 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
 		};
 
 		bus_disp1_opp_table: opp_table14 {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
       [not found]   ` <CGME20190715124455eucas1p13bfc0c1d113225db9607e4c0dbac353c@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17 10:10       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
are not possible to set are removed and new one is added.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1097fa758d9e..f8c36ff0d4c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1135,12 +1135,9 @@
 				opp-hz = /bits/ 64 <67000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <75000000>;
+				opp-hz = /bits/ 64 <80000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <86000000>;
-			};
-			opp03 {
 				opp-hz = /bits/ 64 <100000000>;
 			};
 		};
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
       [not found]   ` <CGME20190715124456eucas1p2acf15d00e3fa7b77fe3a2b10ce1ab74f@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  2019-07-17 10:15       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

This is the most important bus in the Exynos5x SoC. The whole communication
inside SoC does through that bus (apart from direct requests from CCI to
DRAM controller). It is also modeled as a master bus in devfreq framework.
It is also the only one OPP table throughout other buses which has voltage
values. The devfreq software controls the speed of that bus and other
buses. The other buses follows the rate of the master. There is only one
regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
this frequency. However, due to the fact that the other buses follows the
WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
the children frequency should be stable with the set voltage.
It could cause random faults very hard to debug.
Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
working. The new lowest OPP has voltage high enough for buses working up
to 333MHz. It also changes the frequencies of the OPPs to align them to
PLL value such that it is possible to set them using only a divider without
reprogramming OPP. Reprogramming the PLL was not set, so the real frequency
values were not the one from the OPP table, which could confuse the
governor algorithms which relay on OPP speed values making the system to
behave weird.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f8c36ff0d4c3..a355c76af5a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1107,22 +1107,18 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <84000000>;
-				opp-microvolt = <925000>;
+				opp-hz = /bits/ 64 <150000000>;
+				opp-microvolt = <950000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <111000000>;
+				opp-hz = /bits/ 64 <200000000>;
 				opp-microvolt = <950000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <222000000>;
+				opp-hz = /bits/ 64 <300000000>;
 				opp-microvolt = <950000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <333000000>;
-				opp-microvolt = <950000>;
-			};
-			opp04 {
 				opp-hz = /bits/ 64 <400000000>;
 				opp-microvolt = <987500>;
 			};
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 28/50] ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
       [not found]   ` <CGME20190715124457eucas1p1b3033c2505581b350191eed7ba47bb40@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Align the frequencies in OPPs to values which are possible to set using
a divider and parent clock rate. Keep the OPP number in the table equal
or less to the number in bus_wcore (any higher OPPs would not be set).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index a355c76af5a5..3a128cd717e2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1216,7 +1216,7 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <84000000>;
+				opp-hz = /bits/ 64 <110000000>;
 			};
 			opp01 {
 				opp-hz = /bits/ 64 <167000000>;
@@ -1225,9 +1225,6 @@
 				opp-hz = /bits/ 64 <222000000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <300000000>;
-			};
-			opp04 {
 				opp-hz = /bits/ 64 <333000000>;
 			};
 		};
@@ -1236,16 +1233,16 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <67000000>;
+				opp-hz = /bits/ 64 <100000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <133000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <178000000>;
+				opp-hz = /bits/ 64 <200000000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <267000000>;
+				opp-hz = /bits/ 64 <300000000>;
 			};
 		};
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 29/50] ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
       [not found]   ` <CGME20190715124457eucas1p20401b92a7c0eb51af1e0910fbebaa0b5@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Align the OPPs' frequencies to the master clock rate such that the values
are possible to set using only a clock divider. Set max OPP frequency equal
to the max possible for that bus (according to the documentation).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 3a128cd717e2..f2e2e77a86d6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1191,16 +1191,16 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <89000000>;
+				opp-hz = /bits/ 64 <100000000>;
 			};
 			opp01 {
-				opp-hz = /bits/ 64 <133000000>;
+				opp-hz = /bits/ 64 <150000000>;
 			};
 			opp02 {
-				opp-hz = /bits/ 64 <178000000>;
+				opp-hz = /bits/ 64 <200000000>;
 			};
 			opp03 {
-				opp-hz = /bits/ 64 <267000000>;
+				opp-hz = /bits/ 64 <300000000>;
 			};
 		};
 
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800
       [not found]   ` <CGME20190715124458eucas1p2df56f2e0c7a1a0a9144a4d5fbdb471a9@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-17 10:33       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The Exynos5420 SoC had one clock for two lines while Exynos5422/5800 have
dedicated clock tree for the ACLK266_ISP. The max frequency is 300MHz so
it shares the OPP table with bus_gen. The bus is added here and is enabled
in .dts file for proper board.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5800.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319fd65..3b9200db43b6 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -131,3 +131,13 @@
 &mfc {
 	compatible = "samsung,mfc-v8";
 };
+
+&soc {
+		bus_isp266: bus_isp266 {
+			compatible = "samsung,exynos-bus";
+			clocks = <&clock CLK_DOUT_ACLK266_ISP>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_gen_opp_table>;
+			status = "disabled";
+		};
+};
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
       [not found]   ` <CGME20190715124459eucas1p2a1d8795e57a82704ff221567a8810485@eucas1p2.samsung.com>
@ 2019-07-15 12:43     ` Lukasz Luba
  2019-07-17 10:30       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Make the lowest OPP frequency possible to set using a clock divider keeping
in mind the master clock rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f2e2e77a86d6..0be799f843dc 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1250,7 +1250,7 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <75000000>;
+				opp-hz = /bits/ 64 <100000000>;
 			};
 			opp01 {
 				opp-hz = /bits/ 64 <150000000>;
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 32/50] ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
       [not found]   ` <CGME20190715124500eucas1p114c6cbbbb4efa421b2e24d49a6d3d603@eucas1p1.samsung.com>
@ 2019-07-15 12:43     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Align number of OPPs with the number in bus_wcore OPP table.
The higher OPPs would not be set, thus clean them.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0be799f843dc..18c5273091bd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1171,18 +1171,15 @@
 			compatible = "operating-points-v2";
 
 			opp00 {
-				opp-hz = /bits/ 64 <96000000>;
-			};
-			opp01 {
 				opp-hz = /bits/ 64 <111000000>;
 			};
-			opp02 {
+			opp01 {
 				opp-hz = /bits/ 64 <167000000>;
 			};
-			opp03 {
+			opp02 {
 				opp-hz = /bits/ 64 <222000000>;
 			};
-			opp04 {
+			opp03 {
 				opp-hz = /bits/ 64 <333000000>;
 			};
 		};
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
       [not found]   ` <CGME20190715124501eucas1p17382ca9cead8bfe1dc938e6fb583b7c5@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  2019-07-17 10:35       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Change the parents of UART clocks to the CPLL which has 666MHz.
The UARTs' dividers use /10 rate so they would have 66.6MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 18c5273091bd..79f635043247 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1486,6 +1486,8 @@
 &serial_0 {
 	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART0>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma0 13>, <&pdma0 14>;
 	dma-names = "rx", "tx";
 };
@@ -1493,6 +1495,8 @@
 &serial_1 {
 	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART1>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma1 15>, <&pdma1 16>;
 	dma-names = "rx", "tx";
 };
@@ -1500,6 +1504,8 @@
 &serial_2 {
 	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART2>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma0 15>, <&pdma0 16>;
 	dma-names = "rx", "tx";
 };
@@ -1507,6 +1513,8 @@
 &serial_3 {
 	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 	clock-names = "uart", "clk_uart_baud0";
+	assigned-clocks = <&clock CLK_MOUT_UART3>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	dmas = <&pdma1 17>, <&pdma1 18>;
 	dma-names = "rx", "tx";
 };
-- 
2.17.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 34/50] ARM: dts: exynos: set parent clocks to PWM in Exynos5420
       [not found]   ` <CGME20190715124502eucas1p20a35f8c0f426878e50583fa3402de988@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Change the parent of PWM clock to the CPLL which has 666MHz.
The PWM's divider uses /10 rate so it would set 66.6MHz.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 79f635043247..a361dd5a6036 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1473,6 +1473,8 @@
 
 &pwm {
 	clocks = <&clock CLK_PWM>;
+	assigned-clocks = <&clock CLK_MOUT_PWM>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_CPLL>;
 	clock-names = "timers";
 };
 
-- 
2.17.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 35/50] ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
       [not found]   ` <CGME20190715124502eucas1p1b795c100232b405070f4700e3ca6130b@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

This patch changes speed and parent of NoC WCORE bus to 400MHz. The clock
is now attached to a branch were the root is the DPLL which speed is set to
1200MHz. The OPPs are aligned to this rate accordingly.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..aaf18653d8ac 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -46,6 +46,13 @@
 			<&nocp_mem1_0>, <&nocp_mem1_1>;
 	vdd-supply = <&buck3_reg>;
 	exynos,saturation-ratio = <100>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>,
+			  <&clock CLK_MOUT_SW_ACLK400_WCORE>,
+			  <&clock CLK_DOUT_ACLK400_WCORE>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_WCORE>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 36/50] ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
       [not found]   ` <CGME20190715124503eucas1p1d41112e5c10c4fd21c7aada7bdf8e513@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

This patch changes NOC100 bus to proper parent and proper rate. The OPPs
have been align to reflect this parent and its clock rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index aaf18653d8ac..d460041f716c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -58,6 +58,10 @@
 
 &bus_noc {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK100_NOC>,
+			  <&clock CLK_DOUT_ACLK100_NOC>;
+	assigned-clock-parents = <&clock CLK_FF_DOUT_SPLL2>;
+	assigned-clock-rates = <0>, <100000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
       [not found]   ` <CGME20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  2019-07-17 10:25       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The FSYS bus OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (DPLL to 1200MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d460041f716c..6a82dd175b8a 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -72,6 +72,11 @@
 
 &bus_fsys {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+			  <&clock CLK_DOUT_ACLK200_FSYS>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+	assigned-clock-rates = <0>, <240000000>,<1200000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 38/50] ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
       [not found]   ` <CGME20190715124505eucas1p14e68a537cb53cda2cfd832e59425cd25@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The FSYS2 bus OPP table has been aligned to the new parent rate.  The OPP
table is also shared with bus_fsys. This patch sets the proper parent and
picks the init frequency before the devfreq governor starts working. It
sets also parent rate (DPLL to 1200MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6a82dd175b8a..0e71ba64a4fe 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -82,6 +82,11 @@
 
 &bus_fsys2 {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS2>,
+			  <&clock CLK_DOUT_ACLK200_FSYS2>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+	assigned-clock-rates = <0>, <240000000>,<1200000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 39/50] ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
       [not found]   ` <CGME20190715124506eucas1p2b4e906a88978e3edd875e92b1a9fedc4@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The FSYS APB bus OPP table has been aligned to the new parent rate. This
patch sets the proper parent and picks the init frequency before the
devfreq governor starts working. It sets also parent rate (MPLL to
600MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 0e71ba64a4fe..6225d044d01c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -67,6 +67,11 @@
 
 &bus_fsys_apb {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_PCLK200_FSYS>,
+			  <&clock CLK_DOUT_PCLK200_FSYS>,
+			  <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <200000000>,<600000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 40/50] ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
       [not found]   ` <CGME20190715124507eucas1p17793ab35cd6a64fc5626b751e7f095ee@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_gen OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (MPLL to 600MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6225d044d01c..75664ff6d966 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -102,6 +102,10 @@
 
 &bus_gen {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266>,
+			  <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <300000000>,<600000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 41/50] ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
       [not found]   ` <CGME20190715124508eucas1p2b66d72b7eadd7428063387c6881aca64@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_g2d OPP table has been aligned to the new parent rate. This patch
sets the proper parent and picks the init frequency before the devfreq
governor starts working. It sets also parent rate (MPLL to 600MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 75664ff6d966..198e33cf115f 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -116,6 +116,10 @@
 
 &bus_g2d {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266_G2D>,
+			  <&clock CLK_DOUT_ACLK266_G2D>, <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <300000000>,<600000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 42/50] ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
       [not found]   ` <CGME20190715124508eucas1p2f2e09e296dd4ad97a52a2023ede8ae98@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_mscl OPP table has been aligned to the new parent rate. This patch
sets the proper parents in the clock tree and picks the init frequency
before the devfreq governor starts working. It sets also parent rate (MPLL
to 600MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 198e33cf115f..990fe03fce75 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -103,7 +103,8 @@
 &bus_gen {
 	devfreq = <&bus_wcore>;
 	assigned-clocks = <&clock CLK_MOUT_ACLK266>,
-			  <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+			  <&clock CLK_DOUT_ACLK266>,
+			  <&clock CLK_FOUT_MPLL>;
 	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
 	assigned-clock-rates = <0>, <300000000>,<600000000>;
 	status = "okay";
@@ -155,6 +156,13 @@
 
 &bus_mscl {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_MSCL>,
+			  <&clock CLK_MOUT_SW_ACLK400_MSCL>,
+			  <&clock CLK_DOUT_ACLK400_MSCL>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_MSCL>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
       [not found]   ` <CGME20190715124509eucas1p1f2e44af951158fbef1a245467956ef93@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  2019-07-17 10:02       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Add bus_isp which changes ACLK400_ISP clock speed according to the bus
documentation in the documentation. The bus_isp OPP table has been
aligned to the new parent rate. This patch sets the proper parent and
picks the init frequency before the devfreq governor starts working.
It sets also parent rate (DPLL to 1200MHz).

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 990fe03fce75..852cb3dd495d 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -166,6 +166,18 @@
 	status = "okay";
 };
 
+&bus_isp {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
+			  <&clock CLK_MOUT_SW_ACLK400_ISP>,
+			  <&clock CLK_DOUT_ACLK400_ISP>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_ISP>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&buck6_reg>;
 };
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 44/50] ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
       [not found]   ` <CGME20190715124510eucas1p1a88fcaa3b6175a5dae69e6879a534746@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_gen OPP table has been aligned to the parent rate. This patch sets
the proper initial frequency before the devfreq governor starts working.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 852cb3dd495d..27f6ed323ba1 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -131,6 +131,8 @@
 
 &bus_jpeg {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+	assigned-clock-rates = <300000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 45/50] ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
       [not found]   ` <CGME20190715124511eucas1p2b11ef3a5bc093e686ae5450d16785225@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_disp1_fimd OPP table has been aligned to the new parent rate. This
patch sets the proper frequency before the devfreq governor starts working.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 27f6ed323ba1..2cfe1effe290 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -143,6 +143,8 @@
 
 &bus_disp1_fimd {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+	assigned-clock-rates = <300000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 46/50] ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
       [not found]   ` <CGME20190715124512eucas1p1bd847805f945ada00f2b7952592cc104@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_disp1 OPP table has been aligned to the new parent rate. This patch
sets the proper frequencies before the devfreq governor starts working. It
sets 200MHz to bus ACLK_200_DISP1 which is controlled via CLK_DOUT_ACLK200
and 400MHz to ACLK400_DISP1 which is controlled via CLK_DOUT_ACLK400_DISP1.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2cfe1effe290..fac5659516ad 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -150,6 +150,9 @@
 
 &bus_disp1 {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK200>,
+			  <&clock CLK_DOUT_ACLK400_DISP1>;
+	assigned-clock-rates = <200000000>, <400000000>;
 	status = "okay";
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 47/50] ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
       [not found]   ` <CGME20190715124513eucas1p2c30a951141622994d350df5e61fdaed4@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The bus_gscl_scaler OPP table has been aligned to the new parent rate. This
patch sets the proper frequency before the devfreq governor starts working.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index fac5659516ad..d278339f259c 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -158,6 +158,8 @@
 
 &bus_gscl_scaler {
 	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+	assigned-clock-rates = <300000000>;
 	status = "okay";
 };
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 48/50] ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
       [not found]   ` <CGME20190715124514eucas1p1531a88cfb9b4e2fdb801074963372688@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

On Exynos5422 there is a dedicated clock hierarchy for ACLK_266_ISP which
should be set to proper values to fully use the HW performance.
The old settings left after boot set minimal values to this bus.
In the Exynos5420 the bus is connected to ACLK_266 so there is no need for
aligning the values. In the Exynos5422 the proper hierarchy of these
clocks should be model in the software to use the full HW feature set.
The patch sets proper parent (MPLL) and initial frequency to the bus also
enabling it.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d278339f259c..c770d17141e8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -187,6 +187,17 @@
 	status = "okay";
 };
 
+&bus_isp266 {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266_ISP>,
+			  <&clock CLK_MOUT_USER_ACLK266_ISP>,
+			  <&clock CLK_DOUT_ACLK266_ISP>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>,
+				 <&clock CLK_MOUT_SW_ACLK266_ISP>;
+	assigned-clock-rates = <0>, <0>,<300000000>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&buck6_reg>;
 };
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 49/50] ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
       [not found]   ` <CGME20190715124514eucas1p1dcbbcbac0503980825d5e4ebae32003b@eucas1p1.samsung.com>
@ 2019-07-15 12:44     ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

The patch adds SoC buses support. It also changes connections of the clocks
pinning to the rigth parent. There is also frequency set of the needed
clock to make it working at the right rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5800-peach-pi.dts | 172 ++++++++++++++++++++++
 1 file changed, 172 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index e0f470fe54c8..38edb00c7f1b 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -151,6 +151,163 @@
 	vdd-supply = <&ldo9_reg>;
 };
 
+&bus_wcore {
+	devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
+			<&nocp_mem1_0>, <&nocp_mem1_1>;
+	vdd-supply = <&buck3_reg>;
+	exynos,saturation-ratio = <100>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_WCORE>,
+			  <&clock CLK_MOUT_SW_ACLK400_WCORE>,
+			  <&clock CLK_DOUT_ACLK400_WCORE>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_WCORE>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+	status = "okay";
+};
+
+&bus_noc {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK100_NOC>,
+			  <&clock CLK_DOUT_ACLK100_NOC>;
+	assigned-clock-parents = <&clock CLK_FF_DOUT_SPLL2>;
+	assigned-clock-rates = <0>, <100000000>;
+	status = "okay";
+};
+
+&bus_fsys_apb {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_PCLK200_FSYS>,
+			  <&clock CLK_DOUT_PCLK200_FSYS>,
+			  <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <200000000>,<600000000>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+			  <&clock CLK_DOUT_ACLK200_FSYS>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+	assigned-clock-rates = <0>, <240000000>,<1200000000>;
+	status = "okay";
+};
+
+&bus_fsys2 {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS2>,
+			  <&clock CLK_DOUT_ACLK200_FSYS2>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+	assigned-clock-rates = <0>, <240000000>,<1200000000>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_gen {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266>,
+			  <&clock CLK_DOUT_ACLK266>, <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <300000000>,<600000000>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_g2d {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266_G2D>,
+			  <&clock CLK_DOUT_ACLK266_G2D>,
+			  <&clock CLK_FOUT_MPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>;
+	assigned-clock-rates = <0>, <300000000>,<600000000>;
+	status = "okay";
+};
+
+&bus_g2d_acp {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_jpeg {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+	assigned-clock-rates = <300000000>;
+	status = "okay";
+};
+
+&bus_jpeg_apb {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_disp1_fimd {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+	assigned-clock-rates = <300000000>;
+	status = "okay";
+};
+
+&bus_disp1 {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK200>,
+			  <&clock CLK_DOUT_ACLK400_DISP1>;
+	assigned-clock-rates = <200000000>, <400000000>;
+	status = "okay";
+};
+
+&bus_gscl_scaler {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+	assigned-clock-rates = <300000000>;
+	status = "okay";
+};
+
+&bus_mscl {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_MSCL>,
+			  <&clock CLK_MOUT_SW_ACLK400_MSCL>,
+			  <&clock CLK_DOUT_ACLK400_MSCL>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_MSCL>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+	status = "okay";
+};
+
+&bus_isp {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
+			  <&clock CLK_MOUT_SW_ACLK400_ISP>,
+			  <&clock CLK_DOUT_ACLK400_ISP>,
+			  <&clock CLK_FOUT_DPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
+				 <&clock CLK_DOUT_ACLK400_ISP>;
+	assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
+	status = "okay";
+};
+
+&bus_isp266 {
+	devfreq = <&bus_wcore>;
+	assigned-clocks = <&clock CLK_MOUT_ACLK266_ISP>,
+			  <&clock CLK_MOUT_USER_ACLK266_ISP>,
+			  <&clock CLK_DOUT_ACLK266_ISP>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_MPLL>,
+				 <&clock CLK_MOUT_SW_ACLK266_ISP>;
+	assigned-clock-rates = <0>, <0>,<300000000>;
+	status = "okay";
+};
+
 &clock_audss {
 	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
 	assigned-clock-parents = <&clock CLK_MAU_EPLL>;
@@ -736,6 +893,21 @@
 	bus-width = <4>;
 };
 
+&nocp_mem0_0 {
+	status = "okay";
+};
+
+&nocp_mem0_1 {
+	status = "okay";
+};
+
+&nocp_mem1_0 {
+	status = "okay";
+};
+
+&nocp_mem1_1 {
+	status = "okay";
+};
 
 &pinctrl_0 {
 	pinctrl-names = "default";
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH v1 50/50] ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi
       [not found]   ` <CGME20190715124515eucas1p240a8c61dd62d56cbbd0e4d313be2273e@eucas1p2.samsung.com>
@ 2019-07-15 12:44     ` " Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-15 12:44 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc, linux-clk
  Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
	Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene,
	myungjoo.ham, s.nawrocki, m.szyprowski

Change MMC0 clock settings and set parent to MOUT_SPLL with proper rate.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 38edb00c7f1b..c8e02ecc6627 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -891,6 +891,9 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
+	assigned-clocks = <&clock CLK_MOUT_MMC0>, <&clock CLK_FOUT_SPLL>;
+	assigned-clock-parents = <&clock CLK_MOUT_SCLK_SPLL>;
+	assigned-clock-rates = <0>, <800000000>;
 };
 
 &nocp_mem0_0 {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420 Lukasz Luba
@ 2019-07-16  9:13       ` Chanwoo Choi
  2019-07-18  5:19         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16  9:13 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> Change parent of dout_aclk400_wcore to mout_aclk400_wcore which reflects
> topology described in the RM.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index d353870e7fda..361ee53fc9fc 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -577,7 +577,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  
>  static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
>  	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
> -			"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
> +			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
>  };
>  
>  static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

If possible, you better to send it to stable mailing list
with Fixes information.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl " Lukasz Luba
@ 2019-07-16  9:17       ` Chanwoo Choi
  2019-07-18  5:21         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16  9:17 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

The patch4~patch7 just add the ID to control the clock from DT.
You can squash them to one patch instead of splitting out according to
the type of clock.

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> Add needed IDs to MUXes which are used from DT to properly set clock
> hierarchy.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 361ee53fc9fc..8f1d39cb2f1e 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
>  
>  static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
> -	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
> +	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
> +			SRC_TOP0, 4, 3),
>  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
>  			SRC_TOP0, 16, 3),
>  	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  				TOP_SPARE2, 4, 1),
>  
>  	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
> -	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
> +	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
> +			SRC_TOP0, 4, 2),
>  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>  			SRC_TOP0, 16, 2),
>  	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
> @@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>  
>  	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
>  			SRC_TOP10, 0, 1),
> -	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
> -			SRC_TOP10, 4, 1),
> +	MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
> +			mout_sw_aclk400_mscl_p,	SRC_TOP10, 4, 1),
>  	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
>  			SRC_TOP10, 8, 1),
>  	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks
  2019-07-15 12:43     ` [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks Lukasz Luba
@ 2019-07-16  9:26       ` Chanwoo Choi
  2019-07-18  5:26         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16  9:26 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

You don't need to make the separate patches according to
the type of clock just in order to add the ID by handling them
from devicetree.

Please merge following patches to one patch 
- patch2, patch4~patch7, patch9, patch11, patch12, patch14, patch17
and separate from patch13, patch15, patch16 for adding the ID


On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The patch adds NoC WCORE clock IDs needed used for changing parent of the
> main NoC clock from the DT device.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 16ad498e3f3f..d353870e7fda 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -463,7 +463,8 @@ static const struct samsung_fixed_factor_clock
>  static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
>  	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
> -	MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
> +	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
> +			SRC_TOP0, 16, 3),
>  	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
>  
>  	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  
>  	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
>  	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
> -	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
> +	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
> +			SRC_TOP0, 16, 2),
>  	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
>  
>  	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
> @@ -674,8 +676,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>  			SRC_TOP10, 8, 1),
>  	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
>  			SRC_TOP10, 12, 1),
> -	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
> -			SRC_TOP10, 16, 1),
> +	MUX(CLK_MOUT_SW_ACLK400_WCORE, "mout_sw_aclk400_wcore",
> +			mout_sw_aclk400_wcore_p, SRC_TOP10, 16, 1),
>  	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
>  			SRC_TOP10, 20, 1),
>  	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 13/50] clk: samsung: add DPLL rate table in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 13/50] clk: samsung: add DPLL rate table " Lukasz Luba
@ 2019-07-16  9:31       ` Chanwoo Choi
  2019-07-18  6:01         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16  9:31 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

Also, you better to merge patch13/patch15/patch16 to one patch
in order to add the PLL table for DPLL/MPLL/SPLL.

And I have a question. Are there any use-case to change
the PLL frequency for DPLL/MPLL/SPLL?

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The DPLL has fixed frequency left by the bootloader and it is not possible
> to change it. With this patch the DPLL gets rate table the same for the
> whole  PLL family (similar as APLL, KPLL according to RM) so the frequency
> might be changed to one of the values defined there.
> It is needed for further patches which change the DPLL frequency to feed
> the clocks with proper base.
> It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
> disable master clock, which is then populated higher and tries to disable
> PLL, which casues system crash. The flag is needed for this kind of use
> cases.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 7f8221527633..2395b02ce8c5 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>  	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
>  	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
>  			CLK_SET_RATE_PARENT, 0),
> -	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
> +	MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
> +			SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
>  	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
>  
>  	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
> @@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>  
>  	if (_get_rate("fin_pll") == 24 * MHZ) {
>  		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> +		exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>  		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
>  		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>  	}
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks
  2019-07-15 12:43     ` [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks Lukasz Luba
@ 2019-07-16  9:49       ` Chanwoo Choi
  2019-07-18  6:02         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16  9:49 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

Usually, when developing the clock controller driver,
define the same sequence between the definition sequence in dt-bibing
and clock driver. As I replied, if you squash patches, it is easy.

For example,
This series add clock id as following.
                                                                             
 569         MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group1_p,            
 570                         SRC_TOP0, 0, 2),                                        
 571         MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,          
 572                         SRC_TOP0, 4, 2),                                        
 573         MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,        
 574                         SRC_TOP0, 16, 2),                                       
 575         MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p,            
 576                         SRC_TOP0, 20, 2),          

In case of this code, you can define the IDs as following sequentially:

#define CLK_MOUT_ACLK400_ISP ...
#define CLK_MOUT_ACLK400_MSCL ... 
#define CLK_MOUT_ACLK400_WCORE ...
#define CLK_MOUT_ACLK100_NOC ...


But, this series define the ID as following:
	#define CLK_MOUT_ACLK400_WCORE          662                                     
#define CLK_MOUT_SCLK_DPLL      663                                             
	#define CLK_MOUT_ACLK100_NOC    664                                             
#define CLK_MOUT_ACLK200_FSYS2  665                                             
#define CLK_MOUT_PCLK200_FSYS   666                                             
#define CLK_MOUT_ACLK200_FSYS   667                                             
	#define CLK_MOUT_ACLK400_ISP    668                                             
	#define CLK_MOUT_ACLK400_MSCL   669                                             
#define CLK_MOUT_SCLK_MPLL      700                                             
#define CLK_MOUT_ACLK266        701                                             
#define CLK_MOUT_UART0          702                                             
#define CLK_MOUT_UART1          703                                             
#define CLK_MOUT_UART2          704                                             
#define CLK_MOUT_UART3          7

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> There is a need of new IDs which will be used for modeling proper hierarchy
> in the Exynos54xx SoCs. Previous implementation rely on bootloader
> settings, which are not configuring properly some clocks.
> These IDs provide interface to set proper parents.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  include/dt-bindings/clock/exynos5420.h | 27 +++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 02d5ac469a3d..c37a28eeaf7e 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -230,6 +230,30 @@
>  #define CLK_MOUT_USER_MAU_EPLL	659
>  #define CLK_MOUT_SCLK_SPLL	660
>  #define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
> +#define CLK_MOUT_ACLK400_WCORE		662
> +#define CLK_MOUT_SCLK_DPLL	663
> +#define CLK_MOUT_ACLK100_NOC	664
> +#define CLK_MOUT_ACLK200_FSYS2	665
> +#define CLK_MOUT_PCLK200_FSYS	666
> +#define CLK_MOUT_ACLK200_FSYS	667
> +#define CLK_MOUT_ACLK400_ISP	668
> +#define CLK_MOUT_ACLK400_MSCL	669
> +#define CLK_MOUT_SCLK_MPLL	700
> +#define CLK_MOUT_ACLK266	701
> +#define CLK_MOUT_UART0		702
> +#define CLK_MOUT_UART1		703
> +#define CLK_MOUT_UART2		704
> +#define CLK_MOUT_UART3		705
> +#define CLK_MOUT_SCLK_CPLL	706
> +#define CLK_MOUT_PWM		707
> +#define CLK_MOUT_ACLK266_G2D		708
> +#define CLK_MOUT_SW_ACLK400_WCORE	709
> +#define CLK_MOUT_SW_ACLK400_MSCL	710
> +#define CLK_MOUT_SW_ACLK400_ISP		711
> +#define CLK_MOUT_SW_ACLK266_ISP		712
> +#define CLK_MOUT_USER_ACLK266_ISP	713
> +#define CLK_MOUT_ACLK266_ISP	714
> +#define CLK_MOUT_MMC0		715
>  
>  /* divider clocks */
>  #define CLK_DOUT_PIXEL		768
> @@ -264,8 +288,9 @@
>  #define CLK_FF_DOUT_SPLL2	797
>  #define CLK_DOUT_PCLK_DREX0	798
>  #define CLK_DOUT_PCLK_DREX1	799
> +#define CLK_DOUT_ACLK266_ISP	800
>  
>  /* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		800
> +#define CLK_NR_CLKS		801
>  
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
  2019-07-15 12:43     ` [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x Lukasz Luba
@ 2019-07-16 10:01       ` Chanwoo Choi
  0 siblings, 0 replies; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16 10:01 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

I checked the range of ratio as following: Looks good to me.
But, you better to make it to fix the ratio range without adding ID.
Please merge the code related to adding IDs into one patch.
- Exynos5422 TRM ACLK_100_NOC_RATIO [23:20]
- Exynos5420 TRM ACLK_100_NOC_RATIO [22:20]

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The ACLK100_NOC has different topology in Exynos5420 and 5422/5800.  In
> Exynos5420 this clock divider has 3 bits while in 5422/5800 has 4 bits.
> The patch adds needed dividers in the exynos5800_div_clks, updates
> exynos5x_div_clks and exynos5420_div_clks properly. It also adds IDs to
> manage clocks from DT.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 6164d0ca75e0..c13f34d3d9a1 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -471,7 +471,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  			SRC_TOP0, 4, 3),
>  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
>  			SRC_TOP0, 16, 3),
> -	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
> +	MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_5800_p,
> +			SRC_TOP0, 20, 2),

Please squash this code to the patch which add the IDs.
Actually, it is not related to fix the rate range of clock.

>  
>  	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
>  	MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
> @@ -534,6 +535,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
>  	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>  			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
> +	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
> +				DIV_TOP0, 20, 4),

>  	DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
>  				DIV_TOP8, 12, 3),
>  	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
> @@ -569,7 +572,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  			SRC_TOP0, 4, 2),
>  	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>  			SRC_TOP0, 16, 2),
> -	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
> +	MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p,
> +			SRC_TOP0, 20, 2),

ditto.
Please squash this code to the patch which add the IDs.
Actually, it is not related to fix the rate range of clock.

>  
>  	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
>  	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
> @@ -600,6 +604,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
>  	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>  			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
> +	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
> +			DIV_TOP0, 20, 3),
>  };
>  
>  static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
> @@ -798,8 +804,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
>  			DIV_TOP0, 8, 3),
>  	DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
>  			DIV_TOP0, 12, 3),
> -	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
> -			DIV_TOP0, 20, 3),
>  	DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
>  			DIV_TOP0, 24, 3),
>  	DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
> 

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420
  2019-07-15 12:43     ` [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420 Lukasz Luba
@ 2019-07-16 10:22       ` Chanwoo Choi
  2019-07-18  6:05         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Chanwoo Choi @ 2019-07-16 10:22 UTC (permalink / raw)
  To: Lukasz Luba, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi,

On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
> The ACLK266_ISP has different topology in Exynos5420 and 5422/5800.  In
> Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
> it takes the clock from 2-level mux from ACLK266.  In Exynos5422 there is a
> dedicated clock tree and the PLL can be chosen.  The patch adds needed
> MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
> exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
> DT.
> 
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 9d54856dbcda..5f251279b4c8 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
>  PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
>  					"mout_sclk_mpll", "ff_dout_spll2",
>  					"mout_sclk_spll", "mout_sclk_epll"};
> +PNAME(mout_group17_5800_p)	= { "dout_aclk266_isp", "dout_sclk_sw" };
> +PNAME(mout_group18_5800_p)	= { "dout_osc_div", "mout_sw_aclk266_isp" };
> +PNAME(mout_group19_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
> +					"mout_sclk_mpll", "mout_sclk_ipll"};
>  
>  /* fixed rate clocks generated outside the soc */
>  static struct samsung_fixed_rate_clock
> @@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>  	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>  
> +	MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
> +			SRC_TOP8, 12, 2),
>  	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
>  	MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
>  	MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
> @@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  
>  	MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
>  			SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
> +	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
> +			mout_group18_5800_p, SRC_TOP9, 12, 1),
>  	MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
>  							SRC_TOP9, 16, 1),
>  	MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
> @@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  	MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
>  							SRC_TOP9, 28, 1),
>  
> +	MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
> +			SRC_TOP13, 12, 1),
>  	MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
>  	MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
>  							SRC_TOP13, 20, 1),
> @@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>  static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
>  	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>  			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
> +	DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
> +				DIV_TOP8, 12, 3),
>  	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
>  				DIV_TOP8, 16, 3),
>  	DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
> @@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>  	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
>  	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
>  
> +	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
> +			mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
> +
>  	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
>  			mout_group5_5800_p, SRC_TOP7, 16, 2),
>  	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
> @@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>  			SRC_TOP4, 8, 1),
>  	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
>  			SRC_TOP4, 12, 1),
> -	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
> -			SRC_TOP4, 16, 1),
>  	MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
>  	MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
>  	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
> 

I checked it on Exynos5420/5422 TRM.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table " Lukasz Luba
@ 2019-07-17  8:39       ` Krzysztof Kozlowski
  2019-07-17 10:04         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17  8:39 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The FSYS and FSYS2 buses have similar characteristics and both have max
> frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
> only to FSYS APB bus because APB max frequency is 200MHz.
> The new OPPs for FSYS should increase its performance and related devices.

I do not understand the explanation. You say that there are two buses
- FSYS and FSYS2 - and old OPP table should be used for FSYS APB but
you remove the old one (by renaming). Or which one is the 'old one'
here? The reason is speed... wait, what? Usually DTS should describe
the HW so I imagine that proper opp table should be used for proper
bus. It surprised me that we switch a bus to different OPP table just
because of speed concerns. It should be correctness concern.

Please clarify and reword all this.

I am also not sure how this relates with previous patch - whether you
are fixing independent issues. Maybe because I do not see the issue
fixed... change the commit title and adjust the messages to focus WHY
you are doing it. For small fixes WHAT you are doing is rather obvious
so commit msg (and title) should not focus on it.

Best regards,
Krzysztof

>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 941c58bdd809..c7fc4b829b2a 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -995,7 +995,7 @@
>                         compatible = "samsung,exynos-bus";
>                         clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
>                         clock-names = "bus";
> -                       operating-points-v2 = <&bus_fsys_apb_opp_table>;
> +                       operating-points-v2 = <&bus_fsys_opp_table>;
>                         status = "disabled";
>                 };
>
> @@ -1003,7 +1003,7 @@
>                         compatible = "samsung,exynos-bus";
>                         clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
>                         clock-names = "bus";
> -                       operating-points-v2 = <&bus_fsys2_opp_table>;
> +                       operating-points-v2 = <&bus_fsys_opp_table>;
>                         status = "disabled";
>                 };
>
> @@ -1157,7 +1157,7 @@
>                         };
>                 };
>
> -               bus_fsys2_opp_table: opp_table5 {
> +               bus_fsys_opp_table: opp_table5 {
>                         compatible = "operating-points-v2";
>
>                         opp00 {
> --
> 2.17.1
>

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus " Lukasz Luba
@ 2019-07-17  8:48       ` Krzysztof Kozlowski
  2019-07-22 10:47         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17  8:48 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add an OPP for FSYS APB which reflects the real possible frequency.
> The bus will have a new parent clock which speed has 600MHz, thus
> a new possible frequency provided by the clock divider is 150MHz.
> According to the documentation max possible frequency for this bus is
> 200MHz.

Commit msg is good but title could be improved. Focus in the title
what problem/issue you are solving - add intermediate step in scaling
of FSYS APB?

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd " Lukasz Luba
@ 2019-07-17  9:08       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17  9:08 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The lowest OPP must be aligned to possible value after division of parent
> clock rate. Thus, change it to the value which is true for clock 1200MHz.

I think this is getting slightly too granular. It seems you are
solving the same problem (or very small subset of the same problem) as
in patch 22:
https://patchwork.kernel.org/patch/11043849/

Please combine such changes per IP block, unless you have really
reproducible different issues (e.g. reproducible different performance
problem or OOPS, but not just what clk_summary prints). I imagine that
you align entire subsystem (DISP) buses to real clock frequencies (or
to match real frequencies, or to achieve more granular scaling, or to
get slightly better performance).

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
  2019-07-15 12:44     ` [PATCH v1 43/50] ARM: dts: exynos: add bus_isp " Lukasz Luba
@ 2019-07-17 10:02       ` Krzysztof Kozlowski
  2019-07-17 10:12         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:02 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add bus_isp which changes ACLK400_ISP clock speed according to the bus
> documentation in the documentation. The bus_isp OPP table has been
> aligned to the new parent rate.

Title and msg needs fixing.

Please squash it with patch 18.

Best regards,
Krzysztof

> This patch sets the proper parent and
> picks the init frequency before the devfreq governor starts working.
> It sets also parent rate (DPLL to 1200MHz).
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index 990fe03fce75..852cb3dd495d 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -166,6 +166,18 @@
>         status = "okay";
>  };
>
> +&bus_isp {
> +       devfreq = <&bus_wcore>;
> +       assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
> +                         <&clock CLK_MOUT_SW_ACLK400_ISP>,
> +                         <&clock CLK_DOUT_ACLK400_ISP>,
> +                         <&clock CLK_FOUT_DPLL>;
> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
> +                                <&clock CLK_DOUT_ACLK400_ISP>;
> +       assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
> +       status = "okay";
> +};
> +
>  &cpu0 {
>         cpu-supply = <&buck6_reg>;
>  };
> --
> 2.17.1
>

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd " Lukasz Luba
@ 2019-07-17 10:04       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:04 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> According to the documentation max frequency for ACLK300_DISP1 is 300MHz.
> Add an OPP which makes it possible to use the full performance when needed.

Squash it with #23.

BR,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
  2019-07-17  8:39       ` Krzysztof Kozlowski
@ 2019-07-17 10:04         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:04 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

Hi Krzysztof,

On 7/17/19 10:39 AM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The FSYS and FSYS2 buses have similar characteristics and both have max
>> frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
>> only to FSYS APB bus because APB max frequency is 200MHz.
>> The new OPPs for FSYS should increase its performance and related devices.
> 
> I do not understand the explanation. You say that there are two buses
> - FSYS and FSYS2 - and old OPP table should be used for FSYS APB but
> you remove the old one (by renaming). Or which one is the 'old one'
> here? The reason is speed... wait, what? Usually DTS should describe
> the HW so I imagine that proper opp table should be used for proper
> bus. It surprised me that we switch a bus to different OPP table just
> because of speed concerns. It should be correctness concern.
> 
> Please clarify and reword all this.
> 
> I am also not sure how this relates with previous patch - whether you
> are fixing independent issues. Maybe because I do not see the issue
> fixed... change the commit title and adjust the messages to focus WHY
> you are doing it. For small fixes WHAT you are doing is rather obvious
> so commit msg (and title) should not focus on it.

I don't know how familiar you are with AMBA standard or general concept
of NoC, so I am not sure if the explanation below would be sufficient.
There are 3 buses: FSYS, FSYS2, FSYS APB. The first two are connecting
AXI Slave/Master interfaces of the IP blocks. They are dedicated to
transfer the data i.e. to MMC block using 128 bit bus width and 240MHz
clock. The 3rd is dedicated for accessing peripheral registers -
connecting to IP block interfaces called APB3 slave.
As I mentioned in the comment the FSYS and FSYS2 are able to run faster
than the APB bus.
Thus, changing the old implementation which pinned FSYS and FSYS APB
to the same OPP table is wrong. The right connection made by OPP
reference should be FSYS and FSYS2 with also 240MHz max freq inside.

I have discussed offline with Bartek and I will squash DT patches to
an atomic-change-with-OPPs-and-PLL-rate-for-all-children, with more
detailed comment in the commit message describing the old state and the
new one.

Thank you for the review.

Regards,
Lukasz

> 
> Best regards,
> Krzysztof
> 
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index 941c58bdd809..c7fc4b829b2a 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -995,7 +995,7 @@
>>                          compatible = "samsung,exynos-bus";
>>                          clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
>>                          clock-names = "bus";
>> -                       operating-points-v2 = <&bus_fsys_apb_opp_table>;
>> +                       operating-points-v2 = <&bus_fsys_opp_table>;
>>                          status = "disabled";
>>                  };
>>
>> @@ -1003,7 +1003,7 @@
>>                          compatible = "samsung,exynos-bus";
>>                          clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
>>                          clock-names = "bus";
>> -                       operating-points-v2 = <&bus_fsys2_opp_table>;
>> +                       operating-points-v2 = <&bus_fsys_opp_table>;
>>                          status = "disabled";
>>                  };
>>
>> @@ -1157,7 +1157,7 @@
>>                          };
>>                  };
>>
>> -               bus_fsys2_opp_table: opp_table5 {
>> +               bus_fsys_opp_table: opp_table5 {
>>                          compatible = "operating-points-v2";
>>
>>                          opp00 {
>> --
>> 2.17.1
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs " Lukasz Luba
@ 2019-07-17 10:10       ` Krzysztof Kozlowski
  2019-07-17 10:27         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:10 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
> are not possible to set are removed and new one is added.

I think it is just NOC bus... or are there more of such and this is 100 MHz one?

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
  2019-07-17 10:02       ` Krzysztof Kozlowski
@ 2019-07-17 10:12         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:12 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski


On 7/17/19 12:02 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> Add bus_isp which changes ACLK400_ISP clock speed according to the bus
>> documentation in the documentation. The bus_isp OPP table has been
>> aligned to the new parent rate.
> 
> Title and msg needs fixing.
> 
> Please squash it with patch 18.
You are right, it needs to be squashed. As I mentioned earlier Barek
suggested offline to make 'atomic modifications' of OPPs and PLL/clocks
rates for all affected children in the clock tree.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
>> This patch sets the proper parent and
>> picks the init frequency before the devfreq governor starts working.
>> It sets also parent rate (DPLL to 1200MHz).
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> index 990fe03fce75..852cb3dd495d 100644
>> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> @@ -166,6 +166,18 @@
>>          status = "okay";
>>   };
>>
>> +&bus_isp {
>> +       devfreq = <&bus_wcore>;
>> +       assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
>> +                         <&clock CLK_MOUT_SW_ACLK400_ISP>,
>> +                         <&clock CLK_DOUT_ACLK400_ISP>,
>> +                         <&clock CLK_FOUT_DPLL>;
>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
>> +                                <&clock CLK_DOUT_ACLK400_ISP>;
>> +       assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
>> +       status = "okay";
>> +};
>> +
>>   &cpu0 {
>>          cpu-supply = <&buck6_reg>;
>>   };
>> --
>> 2.17.1
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore " Lukasz Luba
@ 2019-07-17 10:15       ` Krzysztof Kozlowski
  2019-07-17 10:29         ` Lukasz Luba
  2019-07-17 16:58         ` Lukasz Luba
  0 siblings, 2 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:15 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> This is the most important bus in the Exynos5x SoC. The whole communication
> inside SoC does through that bus (apart from direct requests from CCI to
> DRAM controller). It is also modeled as a master bus in devfreq framework.
> It is also the only one OPP table throughout other buses which has voltage
> values. The devfreq software controls the speed of that bus and other
> buses. The other buses follows the rate of the master. There is only one
> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for

s/lowest/slowest/

> this frequency. However, due to the fact that the other buses follows the
> WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
> the children frequency should be stable with the set voltage.
> It could cause random faults very hard to debug.
> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs

s/lowest/slowest/

> working. The new lowest OPP has voltage high enough for buses working up
> to 333MHz. It also changes the frequencies of the OPPs to align them to
> PLL value such that it is possible to set them using only a divider without
> reprogramming OPP.

Reprogramming OPP? What is it?

> Reprogramming the PLL was not set, so the real frequency

I understood from the previous that reprogramming the OPP (PLL?) was
happening... Please rephrase entire sentence.

BR,
Krzysztof

> values were not the one from the OPP table, which could confuse the
> governor algorithms which relay on OPP speed values making the system to
> behave weird.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index f8c36ff0d4c3..a355c76af5a5 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -1107,22 +1107,18 @@
>                         compatible = "operating-points-v2";
>
>                         opp00 {
> -                               opp-hz = /bits/ 64 <84000000>;
> -                               opp-microvolt = <925000>;
> +                               opp-hz = /bits/ 64 <150000000>;
> +                               opp-microvolt = <950000>;
>                         };
>                         opp01 {
> -                               opp-hz = /bits/ 64 <111000000>;
> +                               opp-hz = /bits/ 64 <200000000>;
>                                 opp-microvolt = <950000>;
>                         };
>                         opp02 {
> -                               opp-hz = /bits/ 64 <222000000>;
> +                               opp-hz = /bits/ 64 <300000000>;
>                                 opp-microvolt = <950000>;
>                         };
>                         opp03 {
> -                               opp-hz = /bits/ 64 <333000000>;
> -                               opp-microvolt = <950000>;
> -                       };
> -                       opp04 {
>                                 opp-hz = /bits/ 64 <400000000>;
>                                 opp-microvolt = <987500>;
>                         };
> --
> 2.17.1
>

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-15 12:44     ` [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys " Lukasz Luba
@ 2019-07-17 10:25       ` Krzysztof Kozlowski
  2019-07-17 10:38         ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:25 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The FSYS bus OPP table has been aligned to the new parent rate. This patch
> sets the proper parent and picks the init frequency before the devfreq
> governor starts working. It sets also parent rate (DPLL to 1200MHz).

1. I see what the patch is doing, but please write why you are doing
this. What problem are you solving here?
2. Commit title is wrong - it is not Exynos 5422 but Odroid XU3/XU4
family of boards.

>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index d460041f716c..6a82dd175b8a 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -72,6 +72,11 @@
>
>  &bus_fsys {
>         devfreq = <&bus_wcore>;
> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
> +                         <&clock CLK_FOUT_DPLL>;
> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;

Here and in all other patches:
I am not entirely sure that this should be here. It looks like
property of the SoC. Do we expect that buses will be configured to
different clock rates between different boards? Since the OPP tables
are shared (they are property of the SoC, not board) then I would
assume that default frequency is shared as well.

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  2019-07-17 10:10       ` Krzysztof Kozlowski
@ 2019-07-17 10:27         ` Lukasz Luba
  2019-07-17 10:38           ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:27 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski


On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
>> are not possible to set are removed and new one is added.
> 
> I think it is just NOC bus... or are there more of such and this is 100 MHz one?
Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
3 muxes and one divider), which makes possible to take different PLL as
a source then WCORE have, divide the rate from it and even switch for a
while to alternative stable PLL (on the 2nd mux to SPLL (after a
divider)) to wait for main PLL rate change stability delay. Max rate is
limited to 100MHz for this NOC100 bus.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  2019-07-17 10:15       ` Krzysztof Kozlowski
@ 2019-07-17 10:29         ` Lukasz Luba
  2019-07-17 16:58         ` Lukasz Luba
  1 sibling, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:29 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski


On 7/17/19 12:15 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> This is the most important bus in the Exynos5x SoC. The whole communication
>> inside SoC does through that bus (apart from direct requests from CCI to
>> DRAM controller). It is also modeled as a master bus in devfreq framework.
>> It is also the only one OPP table throughout other buses which has voltage
>> values. The devfreq software controls the speed of that bus and other
>> buses. The other buses follows the rate of the master. There is only one
>> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
> 
> s/lowest/slowest/
OK
> 
>> this frequency. However, due to the fact that the other buses follows the
>> WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
>> the children frequency should be stable with the set voltage.
>> It could cause random faults very hard to debug.
>> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
> 
> s/lowest/slowest/
OK
> 
>> working. The new lowest OPP has voltage high enough for buses working up
>> to 333MHz. It also changes the frequencies of the OPPs to align them to
>> PLL value such that it is possible to set them using only a divider without
>> reprogramming OPP.
> 
> Reprogramming OPP? What is it?
Mistake, should be PLL. Thanks for that.
> 
>> Reprogramming the PLL was not set, so the real frequency
> 
> I understood from the previous that reprogramming the OPP (PLL?) was
> happening... Please rephrase entire sentence.
Yes, I will rewrite it when I will combine these patches into one.

Regards,
Lukasz
> 
> BR,
> Krzysztof
> 
>> values were not the one from the OPP table, which could confuse the
>> governor algorithms which relay on OPP speed values making the system to
>> behave weird.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
>>   1 file changed, 4 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index f8c36ff0d4c3..a355c76af5a5 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -1107,22 +1107,18 @@
>>                          compatible = "operating-points-v2";
>>
>>                          opp00 {
>> -                               opp-hz = /bits/ 64 <84000000>;
>> -                               opp-microvolt = <925000>;
>> +                               opp-hz = /bits/ 64 <150000000>;
>> +                               opp-microvolt = <950000>;
>>                          };
>>                          opp01 {
>> -                               opp-hz = /bits/ 64 <111000000>;
>> +                               opp-hz = /bits/ 64 <200000000>;
>>                                  opp-microvolt = <950000>;
>>                          };
>>                          opp02 {
>> -                               opp-hz = /bits/ 64 <222000000>;
>> +                               opp-hz = /bits/ 64 <300000000>;
>>                                  opp-microvolt = <950000>;
>>                          };
>>                          opp03 {
>> -                               opp-hz = /bits/ 64 <333000000>;
>> -                               opp-microvolt = <950000>;
>> -                       };
>> -                       opp04 {
>>                                  opp-hz = /bits/ 64 <400000000>;
>>                                  opp-microvolt = <987500>;
>>                          };
>> --
>> 2.17.1
>>
> 
> 

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
  2019-07-15 12:43     ` [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420 Lukasz Luba
@ 2019-07-17 10:30       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:30 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Make the lowest OPP frequency possible to set using a clock divider keeping
> in mind the master clock rate.

As in previous patch - lowest->slowest. I think OPPs are not
associated with the height or altitude but speed (slow/fast). You
could also add "frequency" which would make it also correct and
specific but slightly longer in title.

Best regards,
Krzysztof

>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index f2e2e77a86d6..0be799f843dc 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -1250,7 +1250,7 @@
>                         compatible = "operating-points-v2";
>
>                         opp00 {
> -                               opp-hz = /bits/ 64 <75000000>;
> +                               opp-hz = /bits/ 64 <100000000>;
>                         };
>                         opp01 {
>                                 opp-hz = /bits/ 64 <150000000>;
> --
> 2.17.1
>

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800
  2019-07-15 12:43     ` [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800 Lukasz Luba
@ 2019-07-17 10:33       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:33 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The Exynos5420 SoC had one clock for two lines while Exynos5422/5800 have
> dedicated clock tree for the ACLK266_ISP. The max frequency is 300MHz so
> it shares the OPP table with bus_gen. The bus is added here and is enabled
> in .dts file for proper board.

Squash it with 48 please.

BR,
Krzysztof

>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  arch/arm/boot/dts/exynos5800.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
> index 57d3b319fd65..3b9200db43b6 100644
> --- a/arch/arm/boot/dts/exynos5800.dtsi
> +++ b/arch/arm/boot/dts/exynos5800.dtsi
> @@ -131,3 +131,13 @@
>  &mfc {
>         compatible = "samsung,mfc-v8";
>  };
> +
> +&soc {
> +               bus_isp266: bus_isp266 {
> +                       compatible = "samsung,exynos-bus";
> +                       clocks = <&clock CLK_DOUT_ACLK266_ISP>;
> +                       clock-names = "bus";
> +                       operating-points-v2 = <&bus_gen_opp_table>;
> +                       status = "disabled";
> +               };
> +};
> --
> 2.17.1
>

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
  2019-07-15 12:44     ` [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs " Lukasz Luba
@ 2019-07-17 10:35       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:35 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Change the parents of UART clocks to the CPLL which has 666MHz.
> The UARTs' dividers use /10 rate so they would have 66.6MHz.

Write also the state before to show what is being fixed (I assume
previous frequency was not best choice).

BR,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  2019-07-17 10:27         ` Lukasz Luba
@ 2019-07-17 10:38           ` Krzysztof Kozlowski
  2019-07-17 10:41             ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:38 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Wed, 17 Jul 2019 at 12:27, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
>
> On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
> > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>
> >> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
> >> are not possible to set are removed and new one is added.
> >
> > I think it is just NOC bus... or are there more of such and this is 100 MHz one?
> Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
> 3 muxes and one divider), which makes possible to take different PLL as
> a source then WCORE have, divide the rate from it and even switch for a
> while to alternative stable PLL (on the 2nd mux to SPLL (after a
> divider)) to wait for main PLL rate change stability delay. Max rate is
> limited to 100MHz for this NOC100 bus.

I think we misunderstood each other. I am saying, that the bus is
called "NOC" in the DTSI. Not NOC100. So unless there are more of
NOCs, stick to existing name NOC, even if it is not the most accurate.

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 10:25       ` Krzysztof Kozlowski
@ 2019-07-17 10:38         ` Lukasz Luba
  2019-07-17 10:45           ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:38 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski



On 7/17/19 12:25 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The FSYS bus OPP table has been aligned to the new parent rate. This patch
>> sets the proper parent and picks the init frequency before the devfreq
>> governor starts working. It sets also parent rate (DPLL to 1200MHz).
> 
> 1. I see what the patch is doing, but please write why you are doing
> this. What problem are you solving here?
> 2. Commit title is wrong - it is not Exynos 5422 but Odroid XU3/XU4
> family of boards.
OK, I will rewrite it when during the work on squashing the patches.
> 
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> index d460041f716c..6a82dd175b8a 100644
>> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> @@ -72,6 +72,11 @@
>>
>>   &bus_fsys {
>>          devfreq = <&bus_wcore>;
>> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
>> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
>> +                         <&clock CLK_FOUT_DPLL>;
>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
>> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
> 
> Here and in all other patches:
> I am not entirely sure that this should be here. It looks like
> property of the SoC. Do we expect that buses will be configured to
> different clock rates between different boards? Since the OPP tables
> are shared (they are property of the SoC, not board) then I would
> assume that default frequency is shared as well.
These clocks they all relay on some bootloader configuration. It depends
which version of the bootloader you have, then you might get different
default configuration in the clocks. The pattern of changing the parent
or even rate is known in the DT files (or I am missing something).
When you grep for it, you get 168 hits (38 for exynos*):
git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l

Regards,
Lukasz

> 
> Best regards,
> Krzysztof
> 
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  2019-07-17 10:38           ` Krzysztof Kozlowski
@ 2019-07-17 10:41             ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 10:41 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski



On 7/17/19 12:38 PM, Krzysztof Kozlowski wrote:
> On Wed, 17 Jul 2019 at 12:27, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>>
>> On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote:
>>> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>>>
>>>> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
>>>> are not possible to set are removed and new one is added.
>>>
>>> I think it is just NOC bus... or are there more of such and this is 100 MHz one?
>> Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with
>> 3 muxes and one divider), which makes possible to take different PLL as
>> a source then WCORE have, divide the rate from it and even switch for a
>> while to alternative stable PLL (on the 2nd mux to SPLL (after a
>> divider)) to wait for main PLL rate change stability delay. Max rate is
>> limited to 100MHz for this NOC100 bus.
> 
> I think we misunderstood each other. I am saying, that the bus is
> called "NOC" in the DTSI. Not NOC100. So unless there are more of
> NOCs, stick to existing name NOC, even if it is not the most accurate.
OK, got it, thanks!

Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 10:38         ` Lukasz Luba
@ 2019-07-17 10:45           ` Krzysztof Kozlowski
  2019-07-17 11:05             ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 10:45 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Wed, 17 Jul 2019 at 12:39, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>
> >>   &bus_fsys {
> >>          devfreq = <&bus_wcore>;
> >> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> >> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
> >> +                         <&clock CLK_FOUT_DPLL>;
> >> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> >> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
> >
> > Here and in all other patches:
> > I am not entirely sure that this should be here. It looks like
> > property of the SoC. Do we expect that buses will be configured to
> > different clock rates between different boards? Since the OPP tables
> > are shared (they are property of the SoC, not board) then I would
> > assume that default frequency is shared as well.
> These clocks they all relay on some bootloader configuration. It depends
> which version of the bootloader you have, then you might get different
> default configuration in the clocks.

I do not agree here. This configuration is not dependent on
bootloader. Although one bootloader might set the clocks to X and
other to Y, but still you provide here valid configuration setting
them, e.g. to Y (or to Z). What bootloader set before does not matter
because you always override it.

> The pattern of changing the parent
> or even rate is known in the DT files (or I am missing something).
> When you grep for it, you get 168 hits (38 for exynos*):
> git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l

Yeah, and if you grep per type you got:
DTSI: 114
DTS: 54
so what do you want to say?

My thinking is that all the boards have buses configured to the same
initial frequency. I am not questioning the use of
assigned-clock-rates at all. Just the place...

BR,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 10:45           ` Krzysztof Kozlowski
@ 2019-07-17 11:05             ` Lukasz Luba
  2019-07-17 11:11               ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 11:05 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski



On 7/17/19 12:45 PM, Krzysztof Kozlowski wrote:
> On Wed, 17 Jul 2019 at 12:39, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>>>
>>>>    &bus_fsys {
>>>>           devfreq = <&bus_wcore>;
>>>> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
>>>> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
>>>> +                         <&clock CLK_FOUT_DPLL>;
>>>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
>>>> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
>>>
>>> Here and in all other patches:
>>> I am not entirely sure that this should be here. It looks like
>>> property of the SoC. Do we expect that buses will be configured to
>>> different clock rates between different boards? Since the OPP tables
>>> are shared (they are property of the SoC, not board) then I would
>>> assume that default frequency is shared as well.
>> These clocks they all relay on some bootloader configuration. It depends
>> which version of the bootloader you have, then you might get different
>> default configuration in the clocks.
> 
> I do not agree here. This configuration is not dependent on
> bootloader. Although one bootloader might set the clocks to X and
> other to Y, but still you provide here valid configuration setting
> them, e.g. to Y (or to Z). What bootloader set before does not matter
> because you always override it.
This exactly the patch set is aim to do: overwrite any bootloader
configuration which could be wrong set after boot.
I don't know for how long it is left in such
'bootloader-default-clock-settings' but it is not accurate
configuration. The pattern in the DT to change the clock rates is
there.

> 
>> The pattern of changing the parent
>> or even rate is known in the DT files (or I am missing something).
>> When you grep for it, you get 168 hits (38 for exynos*):
>> git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l
> 
> Yeah, and if you grep per type you got:
> DTSI: 114
> DTS: 54
> so what do you want to say?
Thus, It could be changed in DT.
> 
> My thinking is that all the boards have buses configured to the same
> initial frequency. I am not questioning the use of
> assigned-clock-rates at all. Just the place...
It is not only 'initial frequency' as you name it. It has three changes:
- re-parent to proper PLL
- changing this PLL rate
- change the OPPs frequency values to integer values derived from PLL

The initial frequencies will be changed by devfreq governor using OPP
tables and the load after the whole system boots.

Regards,
Lukasz
> 
> BR,
> Krzysztof
> 
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 11:05             ` Lukasz Luba
@ 2019-07-17 11:11               ` Krzysztof Kozlowski
  2019-07-17 12:55                 ` Lukasz Luba
  0 siblings, 1 reply; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-17 11:11 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Wed, 17 Jul 2019 at 13:06, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
>
>
> On 7/17/19 12:45 PM, Krzysztof Kozlowski wrote:
> > On Wed, 17 Jul 2019 at 12:39, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>>>
> >>>>    &bus_fsys {
> >>>>           devfreq = <&bus_wcore>;
> >>>> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> >>>> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
> >>>> +                         <&clock CLK_FOUT_DPLL>;
> >>>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> >>>> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
> >>>
> >>> Here and in all other patches:
> >>> I am not entirely sure that this should be here. It looks like
> >>> property of the SoC. Do we expect that buses will be configured to
> >>> different clock rates between different boards? Since the OPP tables
> >>> are shared (they are property of the SoC, not board) then I would
> >>> assume that default frequency is shared as well.
> >> These clocks they all relay on some bootloader configuration. It depends
> >> which version of the bootloader you have, then you might get different
> >> default configuration in the clocks.
> >
> > I do not agree here. This configuration is not dependent on
> > bootloader. Although one bootloader might set the clocks to X and
> > other to Y, but still you provide here valid configuration setting
> > them, e.g. to Y (or to Z). What bootloader set before does not matter
> > because you always override it.
> This exactly the patch set is aim to do: overwrite any bootloader
> configuration which could be wrong set after boot.
> I don't know for how long it is left in such
> 'bootloader-default-clock-settings' but it is not accurate
> configuration. The pattern in the DT to change the clock rates is
> there.

Still it is not the answer to my concerns and questions.

> >
> >> The pattern of changing the parent
> >> or even rate is known in the DT files (or I am missing something).
> >> When you grep for it, you get 168 hits (38 for exynos*):
> >> git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l
> >
> > Yeah, and if you grep per type you got:
> > DTSI: 114
> > DTS: 54
> > so what do you want to say?
> Thus, It could be changed in DT.

Of course, why not. But how this relevant to my question?

> > My thinking is that all the boards have buses configured to the same
> > initial frequency. I am not questioning the use of
> > assigned-clock-rates at all. Just the place...
> It is not only 'initial frequency' as you name it. It has three changes:
> - re-parent to proper PLL
> - changing this PLL rate
> - change the OPPs frequency values to integer values derived from PLL
>
> The initial frequencies will be changed by devfreq governor using OPP
> tables and the load after the whole system boots.

I simplified with "initial frequency" but it does not matter. Let me
try to raise my concerns again, different wording:
All this looks like property of the SoC, not the board, because:
1. the OPPs are already properties of the SoC, not the board (XU3 Lite
is kind of exception but in fact it uses different flavor of
Exynos5422 SoC which we do not model here as separate DTSI),
2. I expect all boards to have the same properties.

Best regards,
Krzysztof

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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 11:11               ` Krzysztof Kozlowski
@ 2019-07-17 12:55                 ` Lukasz Luba
  2019-07-23 12:06                   ` Krzysztof Kozlowski
  0 siblings, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 12:55 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski


On 7/17/19 1:11 PM, Krzysztof Kozlowski wrote:
> On Wed, 17 Jul 2019 at 13:06, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>>
>>
>> On 7/17/19 12:45 PM, Krzysztof Kozlowski wrote:
>>> On Wed, 17 Jul 2019 at 12:39, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>>>>>
>>>>>>     &bus_fsys {
>>>>>>            devfreq = <&bus_wcore>;
>>>>>> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
>>>>>> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
>>>>>> +                         <&clock CLK_FOUT_DPLL>;
>>>>>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
>>>>>> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
>>>>>
>>>>> Here and in all other patches:
>>>>> I am not entirely sure that this should be here. It looks like
>>>>> property of the SoC. Do we expect that buses will be configured to
>>>>> different clock rates between different boards?
This is the board file for Exynos5420/5422/5800 which enables buses.
Thus, I have change them here. Patch 49/50 adds these buses to
Exynos5800 (Peach Pi). In Exynos5420 there is no clock tree for
bus_isp266. The parents for different devices could be also different.
It is because i.e. in 5420 there is 2 bit in the WCORE 1st mux while in
5422 there is 3 bits (6 parents possible).
That's why I have picked exynos5422-odroid-core.dtsi to reference
the bus devices and pinned them into proper parent and changed rate.
When you check patch 49/50 for 5800 not all the parents are the same.

(1) I could create a dedicated files like: exynos5422-bus.dtsi,
exynos5420-bus.dtsi, exynos5800-bus.dtsi which would include some
base file with the basic &bus_X and set the right parent, rate.
Then these files would be included into proper board file like:
exynos5800-peach-pi.dts.
Is this something that you would like to see?
  Since the OPP tables
>>>>> are shared (they are property of the SoC, not board) then I would
>>>>> assume that default frequency is shared as well.
>>>> These clocks they all relay on some bootloader configuration. It depends
>>>> which version of the bootloader you have, then you might get different
>>>> default configuration in the clocks.
>>>
>>> I do not agree here. This configuration is not dependent on
>>> bootloader. Although one bootloader might set the clocks to X and
>>> other to Y, but still you provide here valid configuration setting
>>> them, e.g. to Y (or to Z). What bootloader set before does not matter
>>> because you always override it.
>> This exactly the patch set is aim to do: overwrite any bootloader
>> configuration which could be wrong set after boot.
>> I don't know for how long it is left in such
>> 'bootloader-default-clock-settings' but it is not accurate
>> configuration. The pattern in the DT to change the clock rates is
>> there.
> 
> Still it is not the answer to my concerns and questions.
Please look at my answer above.
> 
>>>
>>>> The pattern of changing the parent
>>>> or even rate is known in the DT files (or I am missing something).
>>>> When you grep for it, you get 168 hits (38 for exynos*):
>>>> git grep -n "assigned-clock-rates" ./arch/arm/boot/dts/ | wc -l
>>>
>>> Yeah, and if you grep per type you got:
>>> DTSI: 114
>>> DTS: 54
>>> so what do you want to say?
>> Thus, It could be changed in DT.
> 
> Of course, why not. But how this relevant to my question?
Please see above.
> 
>>> My thinking is that all the boards have buses configured to the same
>>> initial frequency. I am not questioning the use of
>>> assigned-clock-rates at all. Just the place...
>> It is not only 'initial frequency' as you name it. It has three changes:
>> - re-parent to proper PLL
>> - changing this PLL rate
>> - change the OPPs frequency values to integer values derived from PLL
>>
>> The initial frequencies will be changed by devfreq governor using OPP
>> tables and the load after the whole system boots.
> 
> I simplified with "initial frequency" but it does not matter. Let me
> try to raise my concerns again, different wording:
> All this looks like property of the SoC, not the board, because:
> 1. the OPPs are already properties of the SoC, not the board (XU3 Lite
> is kind of exception but in fact it uses different flavor of
> Exynos5422 SoC which we do not model here as separate DTSI),
Please see above at (1).
> 2. I expect all boards to have the same properties.
All boards which have the same SoC, i.e. Exysno5422 <- then I agree.

Thank you for the comments.

Regards,
Lukasz
> 
> Best regards,
> Krzysztof
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  2019-07-17 10:15       ` Krzysztof Kozlowski
  2019-07-17 10:29         ` Lukasz Luba
@ 2019-07-17 16:58         ` Lukasz Luba
  2019-07-23 12:08           ` Krzysztof Kozlowski
  1 sibling, 1 reply; 90+ messages in thread
From: Lukasz Luba @ 2019-07-17 16:58 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

Hi Krzysztof,

On 7/17/19 12:15 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> This is the most important bus in the Exynos5x SoC. The whole communication
>> inside SoC does through that bus (apart from direct requests from CCI to
>> DRAM controller). It is also modeled as a master bus in devfreq framework.
>> It is also the only one OPP table throughout other buses which has voltage
>> values. The devfreq software controls the speed of that bus and other
>> buses. The other buses follows the rate of the master. There is only one
>> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
> 
> s/lowest/slowest/
please see below
> 
>> this frequency. However, due to the fact that the other buses follows the
>> WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
>> the children frequency should be stable with the set voltage.
>> It could cause random faults very hard to debug.
>> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
> 
> s/lowest/slowest/
Actually, I have double checked that, because we always used this 
terminology: low OPP, high OPP, lower OPPs, higher OPPs. I can change
it here for you, but I think this is not something that people are used
to. Please check EAS pdf documentation or this file:
https://www.kernel.org/doc/Documentation/scheduler/sched-energy.txt
i.e. "running at a lower OPP" or "high OPPs", "lowest OPPs".

Regards,
Lukasz
> 
>> working. The new lowest OPP has voltage high enough for buses working up
>> to 333MHz. It also changes the frequencies of the OPPs to align them to
>> PLL value such that it is possible to set them using only a divider without
>> reprogramming OPP.
> 
> Reprogramming OPP? What is it?
> 
>> Reprogramming the PLL was not set, so the real frequency
> 
> I understood from the previous that reprogramming the OPP (PLL?) was
> happening... Please rephrase entire sentence.
> 
> BR,
> Krzysztof
> 
>> values were not the one from the OPP table, which could confuse the
>> governor algorithms which relay on OPP speed values making the system to
>> behave weird.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
>>   1 file changed, 4 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index f8c36ff0d4c3..a355c76af5a5 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -1107,22 +1107,18 @@
>>                          compatible = "operating-points-v2";
>>
>>                          opp00 {
>> -                               opp-hz = /bits/ 64 <84000000>;
>> -                               opp-microvolt = <925000>;
>> +                               opp-hz = /bits/ 64 <150000000>;
>> +                               opp-microvolt = <950000>;
>>                          };
>>                          opp01 {
>> -                               opp-hz = /bits/ 64 <111000000>;
>> +                               opp-hz = /bits/ 64 <200000000>;
>>                                  opp-microvolt = <950000>;
>>                          };
>>                          opp02 {
>> -                               opp-hz = /bits/ 64 <222000000>;
>> +                               opp-hz = /bits/ 64 <300000000>;
>>                                  opp-microvolt = <950000>;
>>                          };
>>                          opp03 {
>> -                               opp-hz = /bits/ 64 <333000000>;
>> -                               opp-microvolt = <950000>;
>> -                       };
>> -                       opp04 {
>>                                  opp-hz = /bits/ 64 <400000000>;
>>                                  opp-microvolt = <987500>;
>>                          };
>> --
>> 2.17.1
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
  2019-07-16  9:13       ` Chanwoo Choi
@ 2019-07-18  5:19         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  5:19 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi Chanwoo,

On 7/16/19 11:13 AM, Chanwoo Choi wrote:
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> Change parent of dout_aclk400_wcore to mout_aclk400_wcore which reflects
>> topology described in the RM.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index d353870e7fda..361ee53fc9fc 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -577,7 +577,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>>   
>>   static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
>>   	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>> -			"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
>> +			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
>>   };
>>   
>>   static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
>>
> 
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> 
> If possible, you better to send it to stable mailing list
> with Fixes information.
Thank you, I will do it when finish the v2.

Regards,
Lukasz


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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
  2019-07-16  9:17       ` Chanwoo Choi
@ 2019-07-18  5:21         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  5:21 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi Chanwoo,

On 7/16/19 11:17 AM, Chanwoo Choi wrote:
> Hi,
> 
> The patch4~patch7 just add the ID to control the clock from DT.
> You can squash them to one patch instead of splitting out according to
> the type of clock.
Thank you for the review. Yes, you are right it needs to be squashed.

Regards,
Lukasz
> 
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> Add needed IDs to MUXes which are used from DT to properly set clock
>> hierarchy.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 361ee53fc9fc..8f1d39cb2f1e 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
>>   
>>   static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
>> -	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
>> +	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
>> +			SRC_TOP0, 4, 3),
>>   	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
>>   			SRC_TOP0, 16, 3),
>>   	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
>> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>>   				TOP_SPARE2, 4, 1),
>>   
>>   	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
>> -	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
>> +	MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
>> +			SRC_TOP0, 4, 2),
>>   	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>>   			SRC_TOP0, 16, 2),
>>   	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
>> @@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>   
>>   	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
>>   			SRC_TOP10, 0, 1),
>> -	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
>> -			SRC_TOP10, 4, 1),
>> +	MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
>> +			mout_sw_aclk400_mscl_p,	SRC_TOP10, 4, 1),
>>   	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
>>   			SRC_TOP10, 8, 1),
>>   	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks
  2019-07-16  9:26       ` Chanwoo Choi
@ 2019-07-18  5:26         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  5:26 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski



On 7/16/19 11:26 AM, Chanwoo Choi wrote:
> Hi,
> 
> You don't need to make the separate patches according to
> the type of clock just in order to add the ID by handling them
> from devicetree.
> 
> Please merge following patches to one patch
> - patch2, patch4~patch7, patch9, patch11, patch12, patch14, patch17
> and separate from patch13, patch15, patch16 for adding the ID
I agree. The patches will be squashed.

Regards,
Lukasz
> 
> 
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> The patch adds NoC WCORE clock IDs needed used for changing parent of the
>> main NoC clock from the DT device.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 16ad498e3f3f..d353870e7fda 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -463,7 +463,8 @@ static const struct samsung_fixed_factor_clock
>>   static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
>>   	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
>> -	MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
>> +	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
>> +			SRC_TOP0, 16, 3),
>>   	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
>>   
>>   	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
>> @@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>>   
>>   	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
>>   	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
>> -	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
>> +	MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>> +			SRC_TOP0, 16, 2),
>>   	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
>>   
>>   	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
>> @@ -674,8 +676,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>   			SRC_TOP10, 8, 1),
>>   	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
>>   			SRC_TOP10, 12, 1),
>> -	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
>> -			SRC_TOP10, 16, 1),
>> +	MUX(CLK_MOUT_SW_ACLK400_WCORE, "mout_sw_aclk400_wcore",
>> +			mout_sw_aclk400_wcore_p, SRC_TOP10, 16, 1),
>>   	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
>>   			SRC_TOP10, 20, 1),
>>   	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 13/50] clk: samsung: add DPLL rate table in Exynos5420
  2019-07-16  9:31       ` Chanwoo Choi
@ 2019-07-18  6:01         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  6:01 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi Chanwoo,

On 7/16/19 11:31 AM, Chanwoo Choi wrote:
> Hi,
> 
> Also, you better to merge patch13/patch15/patch16 to one patch
> in order to add the PLL table for DPLL/MPLL/SPLL.
OK
> 
> And I have a question. Are there any use-case to change
> the PLL frequency for DPLL/MPLL/SPLL?
Yes, when you set a PLL frequency i.e. DPLL to 1200MHz (from 600MHz)
you can attach a child to it which is running with 400, 300, 150 MHz
and these frequencies are set only on this child clock divider
(/3, /4, /8 - 3bit div) (and there is no set parent rate and
reprogramming the master PLL). While 600MHz cannot satisfy 400MHz
and 300MHz OPPs at the same time.
If the child cannot change the PLL, because it could affect other
children of this PLL and cause misalignment in their frequency after
their dividers, it is better to stick with a rule: pin children to the
PLL with frequency rate which could be divided without a rest and gives
all OPPs rates of all children. This PLL rate could be calculated by
hand, finding least common multiple, keeping in mind clock dividers
width (i.e. 3bit).

That's why I am changing the PLLs' rates and connect children to them
also aligning OPPs to the values which are possible after DIV (3bit).

Regards,
Lukasz

> 
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> The DPLL has fixed frequency left by the bootloader and it is not possible
>> to change it. With this patch the DPLL gets rate table the same for the
>> whole  PLL family (similar as APLL, KPLL according to RM) so the frequency
>> might be changed to one of the values defined there.
>> It is needed for further patches which change the DPLL frequency to feed
>> the clocks with proper base.
>> It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could
>> disable master clock, which is then populated higher and tries to disable
>> PLL, which casues system crash. The flag is needed for this kind of use
>> cases.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 7f8221527633..2395b02ce8c5 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>   	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
>>   	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
>>   			CLK_SET_RATE_PARENT, 0),
>> -	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
>> +	MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p,
>> +			SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0),
>>   	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
>>   
>>   	MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
>> @@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>>   
>>   	if (_get_rate("fin_pll") == 24 * MHZ) {
>>   		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> +		exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>>   		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
>>   		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>>   	}
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks
  2019-07-16  9:49       ` Chanwoo Choi
@ 2019-07-18  6:02         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  6:02 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski



On 7/16/19 11:49 AM, Chanwoo Choi wrote:
> Hi,
> 
> Usually, when developing the clock controller driver,
> define the same sequence between the definition sequence in dt-bibing
> and clock driver. As I replied, if you squash patches, it is easy.
OK
> 
> For example,
> This series add clock id as following.
>                                                                               
>   569         MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group1_p,
>   570                         SRC_TOP0, 0, 2),
>   571         MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
>   572                         SRC_TOP0, 4, 2),
>   573         MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
>   574                         SRC_TOP0, 16, 2),
>   575         MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p,
>   576                         SRC_TOP0, 20, 2),
> 
> In case of this code, you can define the IDs as following sequentially:
> 
> #define CLK_MOUT_ACLK400_ISP ...
> #define CLK_MOUT_ACLK400_MSCL ...
> #define CLK_MOUT_ACLK400_WCORE ...
> #define CLK_MOUT_ACLK100_NOC ...
> 
Thank you for this example. I will align them.

Regards,
Lukasz
> 
> But, this series define the ID as following:
> 	#define CLK_MOUT_ACLK400_WCORE          662
> #define CLK_MOUT_SCLK_DPLL      663
> 	#define CLK_MOUT_ACLK100_NOC    664
> #define CLK_MOUT_ACLK200_FSYS2  665
> #define CLK_MOUT_PCLK200_FSYS   666
> #define CLK_MOUT_ACLK200_FSYS   667
> 	#define CLK_MOUT_ACLK400_ISP    668
> 	#define CLK_MOUT_ACLK400_MSCL   669
> #define CLK_MOUT_SCLK_MPLL      700
> #define CLK_MOUT_ACLK266        701
> #define CLK_MOUT_UART0          702
> #define CLK_MOUT_UART1          703
> #define CLK_MOUT_UART2          704
> #define CLK_MOUT_UART3          7
> 
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> There is a need of new IDs which will be used for modeling proper hierarchy
>> in the Exynos54xx SoCs. Previous implementation rely on bootloader
>> settings, which are not configuring properly some clocks.
>> These IDs provide interface to set proper parents.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   include/dt-bindings/clock/exynos5420.h | 27 +++++++++++++++++++++++++-
>>   1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
>> index 02d5ac469a3d..c37a28eeaf7e 100644
>> --- a/include/dt-bindings/clock/exynos5420.h
>> +++ b/include/dt-bindings/clock/exynos5420.h
>> @@ -230,6 +230,30 @@
>>   #define CLK_MOUT_USER_MAU_EPLL	659
>>   #define CLK_MOUT_SCLK_SPLL	660
>>   #define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
>> +#define CLK_MOUT_ACLK400_WCORE		662
>> +#define CLK_MOUT_SCLK_DPLL	663
>> +#define CLK_MOUT_ACLK100_NOC	664
>> +#define CLK_MOUT_ACLK200_FSYS2	665
>> +#define CLK_MOUT_PCLK200_FSYS	666
>> +#define CLK_MOUT_ACLK200_FSYS	667
>> +#define CLK_MOUT_ACLK400_ISP	668
>> +#define CLK_MOUT_ACLK400_MSCL	669
>> +#define CLK_MOUT_SCLK_MPLL	700
>> +#define CLK_MOUT_ACLK266	701
>> +#define CLK_MOUT_UART0		702
>> +#define CLK_MOUT_UART1		703
>> +#define CLK_MOUT_UART2		704
>> +#define CLK_MOUT_UART3		705
>> +#define CLK_MOUT_SCLK_CPLL	706
>> +#define CLK_MOUT_PWM		707
>> +#define CLK_MOUT_ACLK266_G2D		708
>> +#define CLK_MOUT_SW_ACLK400_WCORE	709
>> +#define CLK_MOUT_SW_ACLK400_MSCL	710
>> +#define CLK_MOUT_SW_ACLK400_ISP		711
>> +#define CLK_MOUT_SW_ACLK266_ISP		712
>> +#define CLK_MOUT_USER_ACLK266_ISP	713
>> +#define CLK_MOUT_ACLK266_ISP	714
>> +#define CLK_MOUT_MMC0		715
>>   
>>   /* divider clocks */
>>   #define CLK_DOUT_PIXEL		768
>> @@ -264,8 +288,9 @@
>>   #define CLK_FF_DOUT_SPLL2	797
>>   #define CLK_DOUT_PCLK_DREX0	798
>>   #define CLK_DOUT_PCLK_DREX1	799
>> +#define CLK_DOUT_ACLK266_ISP	800
>>   
>>   /* must be greater than maximal clock id */
>> -#define CLK_NR_CLKS		800
>> +#define CLK_NR_CLKS		801
>>   
>>   #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
>>
> 
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420
  2019-07-16 10:22       ` Chanwoo Choi
@ 2019-07-18  6:05         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-18  6:05 UTC (permalink / raw)
  To: Chanwoo Choi, devicetree, linux-kernel, linux-arm-kernel,
	linux-samsung-soc, linux-clk
  Cc: mark.rutland, b.zolnierkie, sboyd, mturquette, krzk, a.hajda,
	robh+dt, kyungmin.park, kgene, myungjoo.ham, s.nawrocki,
	m.szyprowski

Hi Chanwoo,

On 7/16/19 12:22 PM, Chanwoo Choi wrote:
> Hi,
> 
> On 19. 7. 15. 오후 9:43, Lukasz Luba wrote:
>> The ACLK266_ISP has different topology in Exynos5420 and 5422/5800.  In
>> Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
>> it takes the clock from 2-level mux from ACLK266.  In Exynos5422 there is a
>> dedicated clock tree and the PLL can be chosen.  The patch adds needed
>> MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
>> exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
>> DT.
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
>>   1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 9d54856dbcda..5f251279b4c8 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
>>   PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
>>   					"mout_sclk_mpll", "ff_dout_spll2",
>>   					"mout_sclk_spll", "mout_sclk_epll"};
>> +PNAME(mout_group17_5800_p)	= { "dout_aclk266_isp", "dout_sclk_sw" };
>> +PNAME(mout_group18_5800_p)	= { "dout_osc_div", "mout_sw_aclk266_isp" };
>> +PNAME(mout_group19_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
>> +					"mout_sclk_mpll", "mout_sclk_ipll"};
>>   
>>   /* fixed rate clocks generated outside the soc */
>>   static struct samsung_fixed_rate_clock
>> @@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
>>   	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>>   
>> +	MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
>> +			SRC_TOP8, 12, 2),
>>   	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
>>   	MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
>>   	MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
>> @@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   
>>   	MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
>>   			SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
>> +	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
>> +			mout_group18_5800_p, SRC_TOP9, 12, 1),
>>   	MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
>>   							SRC_TOP9, 16, 1),
>>   	MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
>> @@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   	MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
>>   							SRC_TOP9, 28, 1),
>>   
>> +	MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
>> +			SRC_TOP13, 12, 1),
>>   	MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
>>   	MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
>>   							SRC_TOP13, 20, 1),
>> @@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
>>   static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
>>   	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
>>   			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
>> +	DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
>> +				DIV_TOP8, 12, 3),
>>   	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
>>   				DIV_TOP8, 16, 3),
>>   	DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
>> @@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>>   	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
>>   	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
>>   
>> +	MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
>> +			mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
>> +
>>   	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
>>   			mout_group5_5800_p, SRC_TOP7, 16, 2),
>>   	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
>> @@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>>   			SRC_TOP4, 8, 1),
>>   	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
>>   			SRC_TOP4, 12, 1),
>> -	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
>> -			SRC_TOP4, 16, 1),
>>   	MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
>>   	MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
>>   	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
>>
> 
> I checked it on Exynos5420/5422 TRM.
> 
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thank you!

Regards,
Lukasz
> 

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
  2019-07-17  8:48       ` Krzysztof Kozlowski
@ 2019-07-22 10:47         ` Lukasz Luba
  0 siblings, 0 replies; 90+ messages in thread
From: Lukasz Luba @ 2019-07-22 10:47 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

Hi Krzysztof,

On 7/17/19 10:48 AM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> Add an OPP for FSYS APB which reflects the real possible frequency.
>> The bus will have a new parent clock which speed has 600MHz, thus
>> a new possible frequency provided by the clock divider is 150MHz.
>> According to the documentation max possible frequency for this bus is
>> 200MHz.
> 
> Commit msg is good but title could be improved. Focus in the title
> what problem/issue you are solving - add intermediate step in scaling
> of FSYS APB?
The devfreq governor for this bus device follows the set OPP of the
master device - WCORE bus and sets the OPP with corresponding ID.
Thus, jumping to max frequency 200MHz when the WCORE bus and other
devices are operating in the middle of their min-max speed is not
needed for FSYS APB and this patch adds the intermediate speed step.

Regards,
Lukasz

> 
> Best regards,
> Krzysztof
> 
> 

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  2019-07-17 12:55                 ` Lukasz Luba
@ 2019-07-23 12:06                   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-23 12:06 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Wed, 17 Jul 2019 at 14:56, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
>
> On 7/17/19 1:11 PM, Krzysztof Kozlowski wrote:
> > On Wed, 17 Jul 2019 at 13:06, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>
> >>
> >>
> >> On 7/17/19 12:45 PM, Krzysztof Kozlowski wrote:
> >>> On Wed, 17 Jul 2019 at 12:39, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>>>>>
> >>>>>>     &bus_fsys {
> >>>>>>            devfreq = <&bus_wcore>;
> >>>>>> +       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> >>>>>> +                         <&clock CLK_DOUT_ACLK200_FSYS>,
> >>>>>> +                         <&clock CLK_FOUT_DPLL>;
> >>>>>> +       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> >>>>>> +       assigned-clock-rates = <0>, <240000000>,<1200000000>;
> >>>>>
> >>>>> Here and in all other patches:
> >>>>> I am not entirely sure that this should be here. It looks like
> >>>>> property of the SoC. Do we expect that buses will be configured to
> >>>>> different clock rates between different boards?
> This is the board file for Exynos5420/5422/5800 which enables buses.
> Thus, I have change them here. Patch 49/50 adds these buses to
> Exynos5800 (Peach Pi). In Exynos5420 there is no clock tree for
> bus_isp266. The parents for different devices could be also different.
> It is because i.e. in 5420 there is 2 bit in the WCORE 1st mux while in
> 5422 there is 3 bits (6 parents possible).
> That's why I have picked exynos5422-odroid-core.dtsi to reference
> the bus devices and pinned them into proper parent and changed rate.
> When you check patch 49/50 for 5800 not all the parents are the same.
>
> (1) I could create a dedicated files like: exynos5422-bus.dtsi,
> exynos5420-bus.dtsi, exynos5800-bus.dtsi which would include some
> base file with the basic &bus_X and set the right parent, rate.
> Then these files would be included into proper board file like:
> exynos5800-peach-pi.dts.
> Is this something that you would like to see?

I see now. Are there any differences in all these properties between
Peach Pi and Odroids? Both of them are using exynos5800.dtsi so that
could be a place for all clock assignments.

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  2019-07-17 16:58         ` Lukasz Luba
@ 2019-07-23 12:08           ` Krzysztof Kozlowski
  0 siblings, 0 replies; 90+ messages in thread
From: Krzysztof Kozlowski @ 2019-07-23 12:08 UTC (permalink / raw)
  To: Lukasz Luba
  Cc: mark.rutland, devicetree, linux-samsung-soc,
	Bartłomiej Żołnierkiewicz, sboyd, mturquette,
	linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi,
	kyungmin.park, kgene, myungjoo.ham, s.nawrocki, linux-clk,
	linux-arm-kernel, Marek Szyprowski

On Wed, 17 Jul 2019 at 18:58, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Hi Krzysztof,
>
> On 7/17/19 12:15 PM, Krzysztof Kozlowski wrote:
> > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
> >>
> >> This is the most important bus in the Exynos5x SoC. The whole communication
> >> inside SoC does through that bus (apart from direct requests from CCI to
> >> DRAM controller). It is also modeled as a master bus in devfreq framework.
> >> It is also the only one OPP table throughout other buses which has voltage
> >> values. The devfreq software controls the speed of that bus and other
> >> buses. The other buses follows the rate of the master. There is only one
> >> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
> >
> > s/lowest/slowest/
> please see below
> >
> >> this frequency. However, due to the fact that the other buses follows the
> >> WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
> >> the children frequency should be stable with the set voltage.
> >> It could cause random faults very hard to debug.
> >> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
> >
> > s/lowest/slowest/
> Actually, I have double checked that, because we always used this
> terminology: low OPP, high OPP, lower OPPs, higher OPPs. I can change
> it here for you, but I think this is not something that people are used
> to. Please check EAS pdf documentation or this file:
> https://www.kernel.org/doc/Documentation/scheduler/sched-energy.txt
> i.e. "running at a lower OPP" or "high OPPs", "lowest OPPs".

Hmm, indeed, you're right. Don't change it then.

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 90+ messages in thread

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Thread overview: 90+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <CGME20190715124433eucas1p2a292f236ea55751117836742c1ca5d23@eucas1p2.samsung.com>
2019-07-15 12:43 ` [PATCH v1 00/50] Exynos5x clocks and buses changes Lukasz Luba
     [not found]   ` <CGME20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks Lukasz Luba
2019-07-16  9:49       ` Chanwoo Choi
2019-07-18  6:02         ` Lukasz Luba
     [not found]   ` <CGME20190715124435eucas1p2099cd7670a3d85d9b11eb0ff86041a2a@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks Lukasz Luba
2019-07-16  9:26       ` Chanwoo Choi
2019-07-18  5:26         ` Lukasz Luba
     [not found]   ` <CGME20190715124436eucas1p28a581bc25f6dae52a5b9b1af26d26368@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420 Lukasz Luba
2019-07-16  9:13       ` Chanwoo Choi
2019-07-18  5:19         ` Lukasz Luba
     [not found]   ` <CGME20190715124437eucas1p1827d7b5d7196f060799e5df6c27d29ad@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl " Lukasz Luba
2019-07-16  9:17       ` Chanwoo Choi
2019-07-18  5:21         ` Lukasz Luba
     [not found]   ` <CGME20190715124437eucas1p2d817f0c1fcf4b523c7910218a6e557d9@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 05/50] clk: samsung: add IDs to aclk400_isp " Lukasz Luba
     [not found]   ` <CGME20190715124438eucas1p2ee9d27c451eb7125bd3ec874baf76e14@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 06/50] clk: samsung: add IDs to ACLK266 clocks " Lukasz Luba
     [not found]   ` <CGME20190715124439eucas1p18c4f512d2647717d77666d94dca867a6@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 07/50] clk: samsung: add IDs to ACLK266_G2D " Lukasz Luba
     [not found]   ` <CGME20190715124440eucas1p10bb25e412f32f0da95761f96831893e6@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420 Lukasz Luba
2019-07-16 10:22       ` Chanwoo Choi
2019-07-18  6:05         ` Lukasz Luba
     [not found]   ` <CGME20190715124441eucas1p12e1f58587318219a5a2c695faa200b17@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x Lukasz Luba
     [not found]   ` <CGME20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x Lukasz Luba
2019-07-16 10:01       ` Chanwoo Choi
     [not found]   ` <CGME20190715124442eucas1p197b23d50f6986477467d23f53b84d187@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124443eucas1p1adf02a02bf77448f2277ddd5fe5e895b@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 12/50] clk: add ID to PWM MUX " Lukasz Luba
     [not found]   ` <CGME20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 13/50] clk: samsung: add DPLL rate table " Lukasz Luba
2019-07-16  9:31       ` Chanwoo Choi
2019-07-18  6:01         ` Lukasz Luba
     [not found]   ` <CGME20190715124445eucas1p1a73385fcbe6205d868ae63b1198ff572@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124446eucas1p1de55fe42ed5555c7a09b10f8c3ec3c3e@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 15/50] clk: samsung: add MPLL rate table in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 16/50] clk: samsung: add SPLL " Lukasz Luba
     [not found]   ` <CGME20190715124447eucas1p143a857f619f48b9b87437ec3b13dfb3f@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 17/50] clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124448eucas1p1b3a8d16d6f5e9fd4ed49c3b7fa66e18e@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 18/50] ARM: dts: exynos: add bus_isp with OPP table Lukasz Luba
     [not found]   ` <CGME20190715124449eucas1p130d853368cb8bf02bef337da2d513fff@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 19/50] ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124450eucas1p189043d196375aa6adacf898de81bfa9b@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table " Lukasz Luba
2019-07-17  8:39       ` Krzysztof Kozlowski
2019-07-17 10:04         ` Lukasz Luba
     [not found]   ` <CGME20190715124451eucas1p2904b49f59cca0cbbc22381f168affbb5@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus " Lukasz Luba
2019-07-17  8:48       ` Krzysztof Kozlowski
2019-07-22 10:47         ` Lukasz Luba
     [not found]   ` <CGME20190715124451eucas1p28ac87fa7bd7e602ffab69a6915f37536@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 22/50] ARM: dts: exynos: OPPs for bus_disp1 " Lukasz Luba
     [not found]   ` <CGME20190715124452eucas1p294d89255359b2036b19213427f558dbf@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd " Lukasz Luba
2019-07-17  9:08       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL " Lukasz Luba
     [not found]   ` <CGME20190715124454eucas1p1cd37552b222539b02629cb52e646ae29@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd " Lukasz Luba
2019-07-17 10:04       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124455eucas1p13bfc0c1d113225db9607e4c0dbac353c@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs " Lukasz Luba
2019-07-17 10:10       ` Krzysztof Kozlowski
2019-07-17 10:27         ` Lukasz Luba
2019-07-17 10:38           ` Krzysztof Kozlowski
2019-07-17 10:41             ` Lukasz Luba
     [not found]   ` <CGME20190715124456eucas1p2acf15d00e3fa7b77fe3a2b10ce1ab74f@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore " Lukasz Luba
2019-07-17 10:15       ` Krzysztof Kozlowski
2019-07-17 10:29         ` Lukasz Luba
2019-07-17 16:58         ` Lukasz Luba
2019-07-23 12:08           ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124457eucas1p1b3033c2505581b350191eed7ba47bb40@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 28/50] ARM: dts: exynos: change OPPs for g2d and g2d_acp buses " Lukasz Luba
     [not found]   ` <CGME20190715124457eucas1p20401b92a7c0eb51af1e0910fbebaa0b5@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 29/50] ARM: dts: exynos: align OPPs of bus_gen " Lukasz Luba
     [not found]   ` <CGME20190715124458eucas1p2df56f2e0c7a1a0a9144a4d5fbdb471a9@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800 Lukasz Luba
2019-07-17 10:33       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124459eucas1p2a1d8795e57a82704ff221567a8810485@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420 Lukasz Luba
2019-07-17 10:30       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124500eucas1p114c6cbbbb4efa421b2e24d49a6d3d603@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 32/50] ARM: dts: exynos: remove lowest OPP from bus_mfc " Lukasz Luba
     [not found]   ` <CGME20190715124501eucas1p17382ca9cead8bfe1dc938e6fb583b7c5@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs " Lukasz Luba
2019-07-17 10:35       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124502eucas1p20a35f8c0f426878e50583fa3402de988@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 34/50] ARM: dts: exynos: set parent clocks to PWM " Lukasz Luba
     [not found]   ` <CGME20190715124502eucas1p1b795c100232b405070f4700e3ca6130b@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 35/50] ARM: dts: exynos: change speed and parent of NoC clock " Lukasz Luba
     [not found]   ` <CGME20190715124503eucas1p1d41112e5c10c4fd21c7aada7bdf8e513@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 36/50] ARM: dts: exynos: change ACLK100_NOC config in Exynos5422 Lukasz Luba
     [not found]   ` <CGME20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys " Lukasz Luba
2019-07-17 10:25       ` Krzysztof Kozlowski
2019-07-17 10:38         ` Lukasz Luba
2019-07-17 10:45           ` Krzysztof Kozlowski
2019-07-17 11:05             ` Lukasz Luba
2019-07-17 11:11               ` Krzysztof Kozlowski
2019-07-17 12:55                 ` Lukasz Luba
2019-07-23 12:06                   ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124505eucas1p14e68a537cb53cda2cfd832e59425cd25@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 38/50] ARM: dts: exynos: change parent and rate of bus_fsys2 " Lukasz Luba
     [not found]   ` <CGME20190715124506eucas1p2b4e906a88978e3edd875e92b1a9fedc4@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 39/50] ARM: dts: exynos: change parent and rate of bus_fsys_acp " Lukasz Luba
     [not found]   ` <CGME20190715124507eucas1p17793ab35cd6a64fc5626b751e7f095ee@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 40/50] ARM: dts: exynos: change parent and rate of bus_gen " Lukasz Luba
     [not found]   ` <CGME20190715124508eucas1p2b66d72b7eadd7428063387c6881aca64@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 41/50] ARM: dts: exynos: change parent and rate of bus_g2d " Lukasz Luba
     [not found]   ` <CGME20190715124508eucas1p2f2e09e296dd4ad97a52a2023ede8ae98@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 42/50] ARM: dts: exynos: change parent and rate of bus_mscl " Lukasz Luba
     [not found]   ` <CGME20190715124509eucas1p1f2e44af951158fbef1a245467956ef93@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 43/50] ARM: dts: exynos: add bus_isp " Lukasz Luba
2019-07-17 10:02       ` Krzysztof Kozlowski
2019-07-17 10:12         ` Lukasz Luba
     [not found]   ` <CGME20190715124510eucas1p1a88fcaa3b6175a5dae69e6879a534746@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 44/50] ARM: dts: exynos: change rate of bus_jpeg " Lukasz Luba
     [not found]   ` <CGME20190715124511eucas1p2b11ef3a5bc093e686ae5450d16785225@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 45/50] ARM: dts: exynos: change rate of bus_disp1_fimd " Lukasz Luba
     [not found]   ` <CGME20190715124512eucas1p1bd847805f945ada00f2b7952592cc104@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 46/50] ARM: dts: exynos: change rates of bus_disp1 " Lukasz Luba
     [not found]   ` <CGME20190715124513eucas1p2c30a951141622994d350df5e61fdaed4@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 47/50] ARM: dts: exynos: change rate of bus_gscl_scaler " Lukasz Luba
     [not found]   ` <CGME20190715124514eucas1p1531a88cfb9b4e2fdb801074963372688@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 48/50] ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422 Lukasz Luba
     [not found]   ` <CGME20190715124514eucas1p1dcbbcbac0503980825d5e4ebae32003b@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 49/50] ARM: dts: exynos: add buses support for Exynos5800 Peach Pi Lukasz Luba
     [not found]   ` <CGME20190715124515eucas1p240a8c61dd62d56cbbd0e4d313be2273e@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 50/50] ARM: dts: exynos: change MMC0 clock parent in " Lukasz Luba

Linux-ARM-Kernel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \
		linux-arm-kernel@lists.infradead.org infradead-linux-arm-kernel@archiver.kernel.org
	public-inbox-index linux-arm-kernel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox