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Fri, 23 Sep 2022 04:20:22 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 23 Sep 2022 04:20:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 23 Sep 2022 04:20:21 -0500 Received: from [172.24.147.145] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28N9KJZ7017226; Fri, 23 Sep 2022 04:20:20 -0500 Subject: Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support To: Matt Ranostay , , CC: , References: <20220909201607.3835-1-mranostay@ti.com> <20220909201607.3835-2-mranostay@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Fri, 23 Sep 2022 14:50:19 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20220909201607.3835-2-mranostay@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220923_022028_623545_0BD11F12 X-CRM114-Status: GOOD ( 16.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Matt, On 10/09/22 1:46 am, Matt Ranostay wrote: > Increase LANE_COUNT_MASK to two-bit field that allows selection of > 4x lane PCIe which was previously limited to 2x lane support. > > Cc: Kishon Vijay Abraham I > Signed-off-by: Matt Ranostay > Signed-off-by: Vignesh Raghavendra > --- > drivers/pci/controller/cadence/pci-j721e.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index a82f845cc4b5..62c2c70256b8 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -43,7 +43,7 @@ enum link_status { > }; > > #define J721E_MODE_RC BIT(7) > -#define LANE_COUNT_MASK BIT(8) > +#define LANE_COUNT_MASK GENMASK(9, 8) The MASK value as well has to be specific to platforms. For J721E, it is 1 bit only. Thanks, Kishon > #define LANE_COUNT(n) ((n) << 8) > > #define GENERATION_SEL_MASK GENMASK(1, 0) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel