From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 895D5C4338F for ; Fri, 20 Aug 2021 13:32:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5253F61130 for ; Fri, 20 Aug 2021 13:32:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5253F61130 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=4o3IGl0TemdZGYtqauT1dJikoNUXC7bHesQLv7nqrjc=; b=C5at2ZuA2YYRYbDthEGWdmzk1x leskdoeAwCPAUfU7c5pxHKIW+d1omxBV27L1WuYCleV3T7FYYsXaXHJQmAhirgMXQKdJZxXzYWo8z JP4VVkVvojXFmU8stPiaCkeC81ROwItchveRDg0hXJoGzcp7cyKuTsMQjzL2X6pv3CUsNQvOdiTIK y61IiyvsUr7YMMi07VX6QbIK10tqft8i5EpW7RchbRAnU1ITwjI7vbPDdOR/LbO0v6JePH4IDIVjN k4RicbuEIBgKFuLCkpPHv8XaAlIf516dsGKiIu6oK3brZztdIfQi5mMKu24dG8hzbeXrmm/OTYpaH C2AkQflA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH4bS-00BIDG-Jl; Fri, 20 Aug 2021 13:30:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH4bO-00BIBq-D8 for linux-arm-kernel@lists.infradead.org; Fri, 20 Aug 2021 13:30:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5205C11FB; Fri, 20 Aug 2021 06:30:25 -0700 (PDT) Received: from [192.168.0.110] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B8E43F66F; Fri, 20 Aug 2021 06:30:24 -0700 (PDT) Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used To: Chen-Yu Tsai , Thomas Gleixner , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210811171505.1502090-1-wenst@chromium.org> From: Alexandru Elisei Message-ID: Date: Fri, 20 Aug 2021 14:31:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210811171505.1502090-1-wenst@chromium.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_063030_651387_7C051713 X-CRM114-Status: GOOD ( 27.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, Pending Marc's testing (I realized I don't have any hardware to test this on at the moment), this patch looks correct to me. One comment below. On 8/11/21 6:15 PM, Chen-Yu Tsai wrote: > When non-secure priorities are used, compared to the raw priority set, > the value read back from RPR is also right-shifted by one and the > highest bit set. > > Add a macro to do the modifications to the raw priority when doing the > comparison against the RPR value. This corrects the pseudo-NMI behavior > when non-secure priorities in the GIC are used. Tested on 5.10 with > the "IPI as pseudo-NMI" series [1] applied on MT8195. > > [1] https://lore.kernel.org/linux-arm-kernel/1604317487-14543-1-git-send-email-sumit.garg@linaro.org/ > > Fixes: 336780590990 ("irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0") > Signed-off-by: Chen-Yu Tsai > --- > drivers/irqchip/irq-gic-v3.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index e0f4debe64e1..e7a0b55413db 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -100,6 +100,15 @@ EXPORT_SYMBOL(gic_pmr_sync); > DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); > EXPORT_SYMBOL(gic_nonsecure_priorities); > > +#define GICD_INT_RPR_PRI(priority) \ > + ({ \ > + u32 __priority = (priority); \ > + if (static_branch_unlikely(&gic_nonsecure_priorities)) \ > + __priority = 0x80 | (__priority >> 1); \ > + \ > + __priority; \ > + }) Would you mind adding a comment to the macro explaining why it's needed? This behaviour is rather subtle and I'm hoping it will save someone's time at some point in the future. I'm thinking something like this (please ignore it if you can think of something better): When the Non-secure world has access to group 0 interrupts (SCR_EL3.FIQ = 0), reading the ICC_RPR_EL1 register will return the Distributor's view of the interrupt priority. When GIC security is enabled (GICD_CTLR.DS = 0), the interrupt priority written by software is moved to the Non-secure range by the Distributor. If both are true (which is the situation where gic_nonsecure_priorities gets enabled), then we need to shift down the priority programmed by software if we want match it against the value returned from ICC_RPR_EL1. With a comment added: Reviewed-by: Alexandru Elisei Thanks, Alex > + > /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ > static refcount_t *ppi_nmi_refs; > > @@ -687,7 +696,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs > return; > > if (gic_supports_nmi() && > - unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { > + unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { > gic_handle_nmi(irqnr, regs); > return; > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel