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Mon, 23 Sep 2019 01:45:57 -0700 (PDT) Subject: Re: [PATCH 3/4] pwm: mxs: add support for inverse polarity To: =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Rasmus Villemoes References: <20190923081348.6843-1-linux@rasmusvillemoes.dk> <20190923081348.6843-4-linux@rasmusvillemoes.dk> <20190923082735.tzxyhvjlnztsxhsc@pengutronix.de> From: Rasmus Villemoes Message-ID: Date: Mon, 23 Sep 2019 10:45:56 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190923082735.tzxyhvjlnztsxhsc@pengutronix.de> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190923_014600_259624_84DC0B0F X-CRM114-Status: GOOD ( 17.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , Thierry Reding , NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 23/09/2019 10.27, Uwe Kleine-K=F6nig wrote: > On Mon, Sep 23, 2019 at 10:13:47AM +0200, Rasmus Villemoes wrote: >> >> = >> + pol_bits =3D state->polarity =3D=3D PWM_POLARITY_NORMAL ? >> + PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; >> + >> writel(duty_cycles << 16, >> mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); >> - writel(PERIOD_PERIOD(period_cycles) | PERIOD_POLARITY_NORMAL | PERIOD_= CDIV(div), >> + writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), > = > When will this affect the output? Only on the next start of a period, or > immediatly? Can it happen that this results in a mixed output (i.e. a > period that has already the new duty cycle from the line above but not > the new polarity (or period)? The data sheet says "Also, when the user reprograms the channel in this manner, the new register values will not take effect until the beginning of a new output period. This eliminates the potential for output glitches that could occur if the registers were updated while the channel was enabled and in the middle of a cycle.". So I think this should be ok. "this manner" refers to the registers being written in the proper order (first ACTIVEn, then PERIODn). Rasmus _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel