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Tue, 21 Jan 2020 18:12:53 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CF97610002A; Tue, 21 Jan 2020 18:12:50 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A85202A8476; Tue, 21 Jan 2020 18:12:50 +0100 (CET) Received: from lmecxl0912.lme.st.com (10.75.127.48) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 21 Jan 2020 18:12:50 +0100 Subject: Re: STM32MP1 level triggered interrupts To: Marek Vasut , Linux ARM , "linux-stm32@st-md-mailman.stormreply.com" References: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> From: Alexandre Torgue Message-ID: Date: Tue, 21 Jan 2020 18:12:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> Content-Language: en-US X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG7NODE2.st.com (10.75.127.20) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.634 definitions=2020-01-21_05:2020-01-21, 2020-01-21 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200121_091300_497508_0896060E X-CRM114-Status: GOOD ( 14.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxime Coquelin , Patrick Delaunay Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek, On 1/20/20 7:32 PM, Marek Vasut wrote: > Hi, > > I have a device connected to STM32MP157C which requires active-low > level-triggered interrupt sink. The device interrupt line is connected > to the SoC gpio-C bank, which has it's interrupt line routed into EXTI, > which can only handle edge triggered interrupts to my understanding. correct. > > However, ARM GIC should be able to do both and EXTI has this irqmux / > EXTImux functionality, which -- if my understanding is correct -- is > capable of routing a select GPIO line directly into the GIC as an EXTIn > interrupt signal. Thus, this might permit handling active low > level-triggered interrupts. Is there some DT binding to configure this yet ? > > Or is there some other, better, way ? > For SPIs, GIC controller handles rising edge triggered interrupt and active high level-sensitive. GIC integration in STM32MP157c makes that only active high level-sensitive configuration for SPI interrupts is supported. Concerning, your question: Setting your gpioC interruption as "falling edge" should be enough. On gpioCx falling edge, a high-level signal is generated by exti and sent to GIC (which triggers GIC interrupt). This signal remains high until stm32_irq_ack is called. So you only need: (ex for gpioc 1). interrupt-parent = <&gpioc>; interrupts = <1 IRQ_TYPE_EDGE_FALLING>; regards Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel