From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
lorenzo.pieralisi@arm.com, mperttunen@nvidia.com,
mmaddireddy@nvidia.com, linux-pci@vger.kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com,
linux-kernel@vger.kernel.org, kthota@nvidia.com, kishon@ti.com,
linux-tegra@vger.kernel.org, robh+dt@kernel.org,
gustavo.pimentel@synopsys.com, jingoohan1@gmail.com,
bhelgaas@google.com, jonathanh@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH V7 05/15] PCI: dwc: Add ext config space capability search API
Date: Tue, 21 May 2019 22:44:04 +0530 [thread overview]
Message-ID: <d70ac7e8-d04e-5195-3808-fca520ad23f6@nvidia.com> (raw)
In-Reply-To: <20190521103629.GE29166@ulmo>
On 5/21/2019 4:06 PM, Thierry Reding wrote:
> On Fri, May 17, 2019 at 06:08:36PM +0530, Vidya Sagar wrote:
>> Add extended configuration space capability search API using struct dw_pcie *
>> pointer
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>> ---
>> Changes since [v6]:
>> * None
>>
>> Changes since [v5]:
>> * None
>>
>> Changes since [v4]:
>> * None
>>
>> Changes since [v3]:
>> * None
>>
>> Changes since [v2]:
>> * None
>>
>> Changes since [v1]:
>> * This is a new patch in v2 series
>>
>> drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
>> drivers/pci/controller/dwc/pcie-designware.h | 1 +
>> 2 files changed, 42 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
>> index 8f53ce63d17e..3b7d50888caa 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware.c
>> @@ -54,6 +54,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
>> }
>> EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
>>
>> +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
>> + int cap)
>
> Perhaps make this more consistent with the existing regular
> configuration space capability search API? Something like this perhaps:
>
> static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci,
> u16 start, u8 cap)
>
> ? I guess your variant above is consistent with the existing generic
> capability search API, so another alternative might be to make the old
> dw_pcie_find_capability() API consistent with everything else. It's
> confusing if we keep having to jump between the two variants.
Ok. I'll change it to the format being followed in this file i.e. using u16 and u8
>
> Thierry
>
>> +{
>> + u32 header;
>> + int ttl;
>> + int pos = PCI_CFG_SPACE_SIZE;
>> +
>> + /* minimum 8 bytes per capability */
>> + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
>> +
>> + if (start)
>> + pos = start;
>> +
>> + header = dw_pcie_readl_dbi(pci, pos);
>> + /*
>> + * If we have no capabilities, this is indicated by cap ID,
>> + * cap version and next pointer all being 0.
>> + */
>> + if (header == 0)
>> + return 0;
>> +
>> + while (ttl-- > 0) {
>> + if (PCI_EXT_CAP_ID(header) == cap && pos != start)
>> + return pos;
>> +
>> + pos = PCI_EXT_CAP_NEXT(header);
>> + if (pos < PCI_CFG_SPACE_SIZE)
>> + break;
>> +
>> + header = dw_pcie_readl_dbi(pci, pos);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
>> +{
>> + return dw_pcie_find_next_ext_capability(pci, 0, cap);
>> +}
>> +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
>> +
>> int dw_pcie_read(void __iomem *addr, int size, u32 *val)
>> {
>> if (!IS_ALIGNED((uintptr_t)addr, size)) {
>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
>> index 6cb978132469..fff284098117 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware.h
>> +++ b/drivers/pci/controller/dwc/pcie-designware.h
>> @@ -252,6 +252,7 @@ struct dw_pcie {
>> container_of((endpoint), struct dw_pcie, ep)
>>
>> u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
>> +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
>>
>> int dw_pcie_read(void __iomem *addr, int size, u32 *val);
>> int dw_pcie_write(void __iomem *addr, int size, u32 val);
>> --
>> 2.17.1
>>
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next prev parent reply other threads:[~2019-05-21 17:14 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-17 12:38 [PATCH V7 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-05-21 10:27 ` Thierry Reding
2019-05-21 16:47 ` Vidya Sagar
2019-05-21 19:34 ` Vidya Sagar
2019-05-21 19:36 ` Bjorn Helgaas
2019-05-22 8:07 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-21 10:29 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-05-21 10:29 ` Thierry Reding
2019-05-21 21:17 ` Bjorn Helgaas
2019-05-22 8:56 ` Vidya Sagar
2019-05-22 14:02 ` Bjorn Helgaas
2019-05-24 14:46 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-05-21 10:36 ` Thierry Reding
2019-05-21 17:14 ` Vidya Sagar [this message]
2019-05-17 12:38 ` [PATCH V7 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-05-21 10:37 ` Thierry Reding
2019-05-24 20:23 ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-05-21 10:38 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-05-21 10:39 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-05-21 10:51 ` Thierry Reding
2019-05-21 18:00 ` Vidya Sagar
2019-05-24 20:26 ` Rob Herring
2019-05-17 12:38 ` [PATCH V7 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-05-21 10:52 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-17 13:03 ` Ard Biesheuvel
2019-05-17 17:38 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-21 10:54 ` Thierry Reding
2019-05-21 18:17 ` Vidya Sagar
2019-05-22 13:48 ` Thierry Reding
2019-05-17 12:38 ` [PATCH V7 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-21 11:00 ` Thierry Reding
2019-05-21 19:37 ` Vidya Sagar
2019-05-21 11:00 ` Thierry Reding
2019-05-22 8:59 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-21 11:41 ` Thierry Reding
2019-05-22 12:05 ` Vidya Sagar
2019-05-22 14:14 ` Thierry Reding
2019-05-24 18:07 ` Vidya Sagar
2019-05-17 12:38 ` [PATCH V7 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
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