From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <robh+dt@kernel.org>, <lee.jones@linaro.org>, <kishon@ti.com>,
<vkoul@kernel.org>, <dan.carpenter@oracle.com>,
<grygorii.strashko@ti.com>, <rogerq@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>, <s-vadapalli@ti.com>
Subject: Re: [PATCH v5 2/3] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200
Date: Tue, 13 Sep 2022 15:15:25 +0530 [thread overview]
Message-ID: <d802f419-f2d6-faca-e0a9-591f4d705b28@ti.com> (raw)
In-Reply-To: <7a673b7c-9e04-2a23-98b9-243696597bba@linaro.org>
Hello Krzysztof,
On 13/09/22 14:57, Krzysztof Kozlowski wrote:
> On 12/09/2022 10:56, Siddharth Vadapalli wrote:
>
>> required:
>> - compatible
>> - reg
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> index 016a37db1ea1..da7cac537e15 100644
>> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> @@ -53,12 +53,25 @@ properties:
>> - ti,am43xx-phy-gmii-sel
>> - ti,dm814-phy-gmii-sel
>> - ti,am654-phy-gmii-sel
>> + - ti,j7200-cpsw5g-phy-gmii-sel
>>
>> reg:
>> maxItems: 1
>>
>> '#phy-cells': true
>>
>> + ti,qsgmii-main-ports:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + description: |
>> + Required only for QSGMII mode. Array to select the port for
>
> Not really an array...
>
>> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>> + ports automatically. Any one of the 4 CPSW5G ports can act as the
>> + main port with the rest of them being the QSGMII_SUB ports.
>> + maxItems: 1
>
>
> You say it is an array, but you have here just one item, so it is just
> uint32. Do you expect it to grow? If so, when? Why it cannot grow now?
Thank you for reviewing the patch.
I have defined it as an array because I plan to reuse this property for
other TI devices like J721e which supports up to two QSGMII main ports.
J7200 on the other hand can have at most one QSGMII main port, which is
why I have restricted the array size to one element as of this series.
In the upcoming patches that I will be posting for J721e, I will be
changing the maxItems to 2 for J721e's compatible while it will continue
to remain 1 for J7200's compatible. This is the reason for defining the
property as an array.
Regards,
Siddharth.
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next prev parent reply other threads:[~2022-09-13 9:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-12 8:56 [PATCH v5 0/3] Add support for QSGMII mode Siddharth Vadapalli
2022-09-12 8:56 ` [PATCH v5 1/3] dt-bindings: phy: ti: phy-gmii-sel: Cleanup example Siddharth Vadapalli
2022-09-13 9:23 ` Krzysztof Kozlowski
2022-09-12 8:56 ` [PATCH v5 2/3] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200 Siddharth Vadapalli
2022-09-13 9:27 ` Krzysztof Kozlowski
2022-09-13 9:45 ` Siddharth Vadapalli [this message]
2022-09-13 10:17 ` Krzysztof Kozlowski
2022-09-12 8:56 ` [PATCH v5 3/3] phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200 Siddharth Vadapalli
2022-09-13 17:40 ` [PATCH v5 0/3] Add support for QSGMII mode Vinod Koul
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