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[81.157.241.155]) by smtp.gmail.com with ESMTPSA id b4sm3541836wma.5.2019.08.22.08.05.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Aug 2019 08:05:57 -0700 (PDT) Subject: Re: [PATCH v2 06/12] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Rob Herring References: <20190806100121.240767-1-maz@kernel.org> <20190806100121.240767-7-maz@kernel.org> From: Julien Message-ID: Date: Thu, 22 Aug 2019 16:05:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <20190806100121.240767-7-maz@kernel.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190822_080600_472056_6935D7C4 X-CRM114-Status: GOOD ( 23.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lokesh Vutla , John Garry , linux-kernel@vger.kernel.org, Shameerali Kolothum Thodi , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 06/08/19 11:01, Marc Zyngier wrote: > As we're about to have a variable number of PPIs, let's make the > allocation of the NMI refcounts dynamic. Also apply some minor > cleanups (moving things around). > > Signed-off-by: Marc Zyngier Reviewed-by: Julien Thierry Thanks, > --- > drivers/irqchip/irq-gic-v3.c | 47 ++++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 13 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index e03fb6d7c2ce..4253c7f67c86 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -88,7 +88,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); > static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); > > /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ > -static refcount_t ppi_nmi_refs[16]; > +static refcount_t *ppi_nmi_refs; > > static struct gic_kvm_info gic_v3_kvm_info; > static DEFINE_PER_CPU(bool, has_rss); > @@ -409,6 +409,16 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio) > writeb_relaxed(prio, base + offset + index); > } > > +static u32 gic_get_ppi_index(struct irq_data *d) > +{ > + switch (get_intid_range(d)) { > + case PPI_RANGE: > + return d->hwirq - 16; > + default: > + unreachable(); > + } > +} > + > static int gic_irq_nmi_setup(struct irq_data *d) > { > struct irq_desc *desc = irq_to_desc(d->irq); > @@ -429,10 +439,12 @@ static int gic_irq_nmi_setup(struct irq_data *d) > return -EINVAL; > > /* desc lock should already be held */ > - if (gic_irq(d) < 32) { > + if (gic_irq_in_rdist(d)) { > + u32 idx = gic_get_ppi_index(d); > + > /* Setting up PPI as NMI, only switch handler for first NMI */ > - if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { > - refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); > + if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { > + refcount_set(&ppi_nmi_refs[idx], 1); > desc->handle_irq = handle_percpu_devid_fasteoi_nmi; > } > } else { > @@ -464,9 +476,11 @@ static void gic_irq_nmi_teardown(struct irq_data *d) > return; > > /* desc lock should already be held */ > - if (gic_irq(d) < 32) { > + if (gic_irq_in_rdist(d)) { > + u32 idx = gic_get_ppi_index(d); > + > /* Tearing down NMI, only switch handler for last NMI */ > - if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) > + if (refcount_dec_and_test(&ppi_nmi_refs[idx])) > desc->handle_irq = handle_percpu_devid_irq; > } else { > desc->handle_irq = handle_fasteoi_irq; > @@ -1394,7 +1408,19 @@ static void gic_enable_nmi_support(void) > { > int i; > > - for (i = 0; i < 16; i++) > + if (!gic_prio_masking_enabled()) > + return; > + > + if (gic_has_group0() && !gic_dist_security_disabled()) { > + pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); > + return; > + } > + > + ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); > + if (!ppi_nmi_refs) > + return; > + > + for (i = 0; i < gic_data.ppi_nr; i++) > refcount_set(&ppi_nmi_refs[i], 0); > > static_branch_enable(&supports_pseudo_nmis); > @@ -1472,12 +1498,7 @@ static int __init gic_init_bases(void __iomem *dist_base, > gicv2m_init(handle, gic_data.domain); > } > > - if (gic_prio_masking_enabled()) { > - if (!gic_has_group0() || gic_dist_security_disabled()) > - gic_enable_nmi_support(); > - else > - pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); > - } > + gic_enable_nmi_support(); > > return 0; > > -- Julien Thierry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel